Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-114 Freescale Semiconductor
Algorithm Boolean CheckPreviousBit(siTD.C-prog-mask, siTD.C-mask, cMicroFrameBit)
Begin
Boolean rvalue = TRUE;
previousBit = cMicroFrameBit rotate-right(1)
-- Bit-wise anding previousBit with C-mask indicates whether there
-- was an intent to send a complete split in the previous micro-
-- frame. So, if the 'previous bit' is set in C-mask, check
-- C-prog-mask to make sure it happened.
if previousBit bitAND siTD.C-mask then
if not (previousBit bitAND siTD.C-prog-mask) then
rvalue = FALSE
End if
End if
Return rvalue
End Algorithm
If Test A is true and FRINDEX[2–0] is zero or one, this is a case 2a or 2b scheduling boundary (see
Figure 13-57). See Section 13.6.12.3.6, “Complete-Split for Scheduling Boundary Cases 2a, 2b,” for
details in handling this condition.
If Test A and Test B evaluate to true, the host controller executes a complete-split transaction using the
transfer state of the current siTD. When the host controller commits to executing the complete-split
transaction, it updates QH[C-prog-mask] by bit-ORing with cMicroFrameBit. The transfer state is
advanced based on the completion status of the complete-split transaction. To advance the transfer state of
an IN siTD, the host controller must perform the following actions:
1. Decrement the number of bytes received from siTD[Total Bytes To Transfer]
2. Adjust siTD[Current Offset] by the number of bytes received
3. Adjust the siTD[P] (page select) field if the transfer caused the host controller to use the next page
pointer
4. Set any appropriate bits in the siTD[Status] field, depending on the results of the transaction.
Note that if the host controller encounters a condition where siTD[Total Bytes To Transfer] is zero, and it
receives more data, the host controller must not write the additional data to memory. The
siTD[Status-Active] bit must be cleared and the siTD[Status-Babble Detected] bit must be set. The fields
siTD[Total Bytes To Transfer], siTD[Current Offset], and siTD[P] are not required to be updated as a result
of this transaction attempt.
The host controller accepts (assuming good data packet CRC and sufficient room in the buffer as indicated
by the value of siTD[Total Bytes To Transfer]) MDATA and DATA0/1 data payloads up to and including
192 bytes. The host controller may optionally clear siTD[Status-Active] and set siTD[Status-Babble
Detected] when it receives MDATA or DATA0/1 with a data payload of more than 192 bytes. The
following responses have the noted effects:
•ERR
The full-speed transaction completed with a time-out or bad CRC and this is a reflection of that
error to the host. The host controller sets the ERR bit in the siTD[Status] field and clears the Active
bit.
• Transaction Error (XactErr)