Information

Overview

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

1-4 Freescale Semiconductor

— 128-byte maximum payload size

— Virtual channel 0 only

— Traffic class 0–7

— Full 64-bit decode with 32-bit wide windows

— Four outbound translation address windows

– Support for mapping 32-bit internal local memory space to an external 32- or 64-bit address

space and translating that address within the PCI Express space

— Four inbound translation address windows corresponding to defined PCI Express BARs

– The first BAR is 32-bits can be programmed to use on-chip register access

– The second BAR is 32-bits,which is for general use

– The remaining two BARs may be 32- or 64-bits and are also for general use

• Enhanced local bus controller (eLBC)

— Non-multiplexed 26-bit address and 8-/16-bit data operating at up to 66 MHz

— Four chip selects supporting four external slaves

— Variable memory block sizes (32 Kbytes to 4 Gbytes in FCM mode, 32 Kbytes to 64 Mbytes

in UPM mode, and 32 Kbytes to 64 Mbytes in GPCM mode)

— Supports boot from NOR Flash and NAND Flash

— Supports programmable clock ratio dividers

— Up to eight-beat burst transfers

— 16- and 8-bit ports

— Three protocol engines available on a per-chip select basis:

– General-purpose chip select machine (GPCM)

– Three user programmable machines (UPMs)

– NAND Flash control machine (FCM)

— Default boot ROM chip select with configurable bus width (8 or 16)

— Provides two Write Enable signals to allow single-byte write access to external 16-bit eLBC

slave devices

• Integrated programmable interrupt controller (IPIC)

— Functional and programming compatibility with the MPC8260 interrupt controller

— Support for external and internal discrete interrupt sources

— Programmable highest priority request

— Six groups of interrupts with programmable priority

— External and internal interrupts directed to host processor

— Supports MSI functionality for PCI Express

— Unique vector number for each interrupt source

•Two I

C interfaces

— Two-wire interface

— Multiple-master support