Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-85
Figure 13-50 shows an example illustrating the H-bit in a schedule.
Figure 13-50. Asynchronous Schedule List with Annotation to Mark Head of List
13.6.9.4 Asynchronous Schedule Traversal: Start Event
Once the host controller has idled itself using the empty schedule detection, it naturally activates and
begins processing from the Periodic Schedule at the beginning of each microframe. In addition, it may
have idled itself early in a microframe. When this occurs (idles early in the microframe) the host controller
must occasionally reactivate during the microframe and traverse the asynchronous schedule to determine
whether any progress can be made. Asynchronous schedule Start Events are defined to be:
• Whenever the host controller transitions from the periodic schedule to the asynchronous schedule.
If the periodic schedule is disabled and the asynchronous schedule is enabled, then the beginning
of the microframe is equivalent to the transition from the periodic schedule, or
• The asynchronous schedule traversal restarts from a sleeping state.
13.6.9.5 Reclamation Status Bit (USBSTS Register)
The operation of the empty asynchronous schedule detection feature depends on the proper management
of the Reclamation bit (RCL) in the USBSTS register. The host controller tests for an empty schedule just
after it fetches a new queue head while traversing the asynchronous schedule. The host controller sets
USBSTS[RCL] whenever an asynchronous schedule traversal Start Event occurs. USBSTS[RCL] is also
set whenever the host controller executes a transaction while traversing the asynchronous schedule.The
host controller clears USBSTS[RCL] whenever it finds a queue head with its H-bit set. Software should
only set a queue head's H-bit if the queue head is in the asynchronous schedule. If software sets the H-bit
in an interrupt queue head, the resulting behavior is undefined. The host controller may clear
USBSTS[RCL] when executing from the periodic schedule.
13.6.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads
This section presents an overview of how the host controller interacts with queuing data structures.
USBSTS
Reclamation Flag
USBCMD
•
•
•
AsyncListAddr 01Horizontal Ptr 0
1
H
•
•
•
Operational
Registers
Operational
Area
Horizontal Ptr
0
H
Operational
Area
0
H
Operational
Area
Typ T
01
0
Typ T
01 0
Typ T
Horizontal Ptr
List Head
Asynchronous Schedule
1: Transaction Executed
0: Head of List Seen