Information

Overview
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
1-2 Freescale Semiconductor
— Enhanced version of the MPC603e core
— High-performance, superscalar processor core with a four-stage pipeline and low interrupt
latency times
— Floating-point, dual integer units, load/store, system register, and branch processing units
— 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities
— Capable of completing two MACs every three cycles
— Dynamic power management
— Enhanced hardware program debug features
— Software-compatible with Freescale processor families implementing Power Architecture
technology
— Separate PLL that is clocked by the system bus clock
— Performance monitor
• DDR SDRAM memory controller
— Programmable timing supporting DDR2 SDRAM
— Integrated SDRAM clock generation
— Supports 8-bit ECC
— 16-/32-bit data interface, up to 266-MHz data rate
— 512-Mbyte addressable space for 32-bit data interface; 256-Mbyte for 16-bit data interface
— The following SDRAM configurations are supported:
– Up to two physical banks (chip selects), each bank up to 1 Gbyte independently addressable
– 64-Mbit to 2-Gbit devices with 8/16 data ports (no direct 4 support)
– One 16-bit device or two 8-bit devices on a 16-bit bus, or two 16-bit devices or four 8-bit
devices on a 32-bit bus
— Support for up to 16 pages for DDR2
— Two chip selects
— Supports auto refresh
— On-the-fly power management using CKE
— Registered DIMM support
— 1.8-V SSTL_18 compatible I/O for DDR2
• Two enhanced three-speed Ethernet controllers (eTSEC)
— Three-speed support (10/100/1000 Mbps)
— MII/RGMII interface
— Controllers designed to comply with IEEE Std 802.3®, 802.3u®, 802.3x®, 802.3z®,
802.3ac®, and 802.3ab®
— TCP/IP acceleration and QoS features available
– IP v4 and IP v6 header recognition on receive
– IP v4 header checksum verification and generation
– TCP and UDP checksum verification and generation