Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-80 Freescale Semiconductor
a page boundary. Doing so yields undefined behavior. The host controller hardware is not required to alias
the page selector to page zero. USB 2.0 isochronous endpoints can specify a period greater than one.
Software can achieve the appropriate scheduling by linking iTDs into the appropriate frames (relative to
the frame list) and by setting appropriate transaction description elements active bits to a one.
13.6.8.2.1 Periodic Scheduling Threshold
The Isochronous Scheduling Threshold field in the HCCPARAMS capability register is an indicator to
system software as to how the host controller pre-fetches and effectively caches schedule data structures.
It is used by system software when adding isochronous work items to the periodic schedule. The value of
this field indicates to system software the minimum distance it can update isochronous data (relative to the
current location of the host controller execution in the periodic list) and still have the host controller
process them.
The iTD and siTD data structures each describe 8 microframes worth of transactions. The host controller
is allowed to cache one (or more) of these data structures in order to reduce memory traffic. There are three
basic caching models that account for the fact the isochronous data structures span 8 microframes. The
three caching models are: no caching, microframe caching and frame caching.
When software is adding new isochronous transactions to the schedule, it always performs a read of the
FRINDEX register to determine the current frame and microframe the host controller is currently
executing. Of course, there is no information about where in the microframe the host controller is, so a
constant uncertainty factor of one microframe has to be assumed. Combining the knowledge of where the
host controller is executing with the knowledge of the caching model allows the definition of simple
algorithms for how closely software can reliably work to the executing host controller.
No caching is indicated with a value of zero in the Isochronous Scheduling Threshold field. The host
controller may pre-fetch data structures during a periodic schedule traversal (per microframe) but will
always dump any accumulated schedule state at the end of the microframe. At the appropriate time relative
to the beginning of every microframe, the host controller always begins schedule traversal from the frame
list. Software can use the value of the FRINDEX register (plus the constant 1 uncertainty-factor) to
determine the approximate position of the executing host controller. When no caching is selected, software
can add an isochronous transaction as near as 2 microframes in front of the current executing position of
the host controller.
Frame caching is indicated with a non-zero value in bit [7] of the Isochronous Scheduling Threshold field.
In the frame-caching model, system software assumes that the host controller caches one (or more)
isochronous data structures for an entire frame (8 microframes). Software uses the value of the FRINDEX
register (plus the constant 1 uncertainty) to determine the current microframe/frame (assume modulo 8
arithmetic in adding the constant 1 to the microframe number). For any current frame N, if the current
microframe is 0 to 6, then software can safely add isochronous transactions to Frame N + 1. If the current
microframe is 7, then software can add isochronous transactions to Frame N + 2.
Microframe caching is indicated with a non-zero value in the least-significant 3 bits of the Isochronous
Scheduling Threshold field. System software assumes the host controller caches one or more periodic data
structures for the number of microframes indicated in the Isochronous Scheduling Threshold field. For
example, if the count value were 2, then the host controller keeps a window of two microframes worth of