Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-77
13.6.8.1 Host Controller Operational Model for iTDs
The host controller uses FRINDEX register bits 12–3 to index into the periodic frame list. This means that
the host controller visits each frame list element eight consecutive times before incrementing to the next
periodic frame list element. Each iTD contains eight transaction descriptions, which map directly to
FRINDEX register bits 2–0. Each iTD can span 8 microframes worth of transactions. When the host
controller fetches an iTD, it uses FRINDEX register bits 2–0 to index into the transaction description array.
When the first iTD in the periodic list is traversed after periodic schedule is enabled, the value of
FRINDEX[2:0] may be other then 0, so the first transaction issued by the controller may be any of the eight
available active transactions. If the active bit in the Status field of the indexed transaction description is
cleared, the host controller ignores the iTD and follows the Next pointer to the next schedule data structure.
When the indexed active bit is a one the host controller continues to parse the iTD. It stores the indexed
transaction description and the general endpoint information (device address, endpoint number, maximum
packet size, etc.). It also uses the Page Select (PG) field to index the buffer pointer array, storing the
selected buffer pointer and the next sequential buffer pointer. For example, if PG field is a 0, then the host
controller will store Page 0 and Page 1.
The host controller constructs a physical data buffer address by concatenating the current buffer pointer
(as selected using the current transaction description's PG field) and the transaction description's
Transaction Offset field. The host controller uses the endpoint addressing information and I/O-bit to
execute a transaction to the appropriate endpoint. When the transaction is complete, the host controller
clears the active bit and writes back any additional status information to the Status field in the currently
selected transaction description.
The data buffer associated with the iTD must be virtually contiguous memory. Seven page pointers are
provided to support eight high-bandwidth transactions regardless of the starting packet’s offset alignment
into the first page. A starting buffer pointer (physical memory address) is constructed by concatenating the
page pointer (example: page 0 pointer) selected by the active transaction descriptions’ PG (example value:
0b00) field with the transaction offset field. As the transaction moves data, the host controller must detect
when an increment of the current buffer pointer will cross a page boundary. When this occurs the host
controller simply replaces the current buffer pointer’s page portion with the next page pointer (example:
page 1 pointer) and continues to move data. The size of each bus transaction is determined by the value in
the Maximum Packet Size field. An iTD supports high-bandwidth pipes via the Mult (multiplier) field.
When the Mult field is 1, 2, or 3, the host controller executes the specified number of Maximum Packet
sized bus transactions for the endpoint in the current microframe. In other words, the Mult field represents
a transaction count for the endpoint in the current microframe. If the Mult field is zero, the operation of
the host controller is undefined. The transfer description is used to service all transactions indicated by the
Mult field.
For OUT transfers, the value of the Transaction n Length field represents the total bytes to be sent during
the microframe. The Mult field must be set by software to be consistent with Transaction n Length and
Maximum Packet Size. The host controller will send the bytes in Maximum Packet Sized portions. After
each transaction, the host controller decrements it's local copy of Transaction n Length by Maximum
Packet Size. The number of bytes the host controller sends is always Maximum Packet Size or Transaction
n Length, whichever is less. The host controller advances the transfer state in the transfer description,