Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-74 Freescale Semiconductor
values are separate, but tightly coupled. The periodic frame list is accessed via the Frame List Index
Register (FRINDEX). Bits FRINDEX[2–0], represent the microframe number. The SOF value is coupled
to the value of FRINDEX[13–3]. Both FRINDEX[13–3] and the SOF value are incremented based on
FRINDEX[2–0]. It is required that the SOF value be delayed from the FRINDEX value by one
microframe. The one microframe delay yields a host controller periodic schedule and bus frame boundary
relationship as illustrated in Figure 13-46. This adjustment allows software to trivially schedule the
periodic start and complete-split transactions for full-and low-speed periodic endpoints, using the natural
alignment of the periodic schedule interface.
Figure 13-46 illustrates how periodic schedule data structures relate to schedule frame boundaries and bus
frame boundaries. To aid the presentation, two terms are defined. The host controller's view of the
1-millisecond boundaries is called H-Frames. The high-speed bus's view of the 1-millisecond boundaries
is called B-Frames.
Figure 13-46. Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries
H-Frame boundaries for the host controller correspond to increments of FRINDEX[13–3]. Microframe
numbers for the H-Frame are tracked by FRINDEX[2–0]. B-Frame boundaries are visible on the
high-speed bus via changes in the SOF token's frame number. Microframe numbers on the high-speed bus
are only derived from the SOF token's frame number (that is, the high-speed bus will see eight SOFs with
the same frame number value). H-Frames and B-Frames have the fixed relationship (that is, B-Frames lag
H-Frames by one microframe time) illustrated in Figure 13-46. The host controller's periodic schedule is
naturally aligned to H-Frames. Software schedules transactions for full- and low-speed periodic endpoints
relative the H-Frames. The result is these transactions execute on the high-speed bus at exactly the right
time for the USB 2.0 hub periodic pipeline. As described in Section 13.3.2.4, “Frame Index Register
(FRINDEX),” the SOF Value can be implemented as a shadow register (in this example, called SOFV),
which lags the FRINDEX register bits [13–3] by one microframe count. Table 13-65 illustrates the
required relationship between the value of FRINDEX and the value of SOFV. This lag behavior can be
accomplished by incrementing FRINDEX[13–3] based on carry-out on the 7 to 0 increment of
FRINDEX[2–0] and incrementing SOFV based on the transition of 0 to 1 of FRINDEX[2–0].
HS Bus
7
CSCSCSCSSS
076543210
HC Periodic Schedule
Frame Boundaries
HC Periodic
Schedule
1
CSCS
10765432 2
SS CS CS
Frames
Micro-Frames
Full/Low-Speed
Transaction
Full/Low-Speed
Transaction
B-Frame N B-Frame N+1
HS/FS/LS Bus
Frame Boundaries
H-Frame N
Interface Data Structure
H-Frame N+1
Interface Data Structure