Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 1-1
Chapter 1
Overview
This document provides an overview of the MPC8308 PowerQUICC II Pro processor features, including
a block diagram showing the major functional components. MPC8308 is a cost-effective, low-power,
highly integrated host processor. The device extends the PowerQUICC family, adding higher CPU
performance, additional functionality, and faster interfaces while addressing the requirements related to
time-to-market, price, power consumption, and package size.
1.1 MPC8308 Overview
Figure 1-1 shows the major functional units within the MPC8308. The Power™ e300 core in the
MPC8308, with its 16 Kbytes of instruction and 16 Kbytes of data cache, implements the PowerPC user
instruction set architecture and provides hardware and software debugging support. In addition, the
MPC8308 offers a PCI Express controller, two three-speed 10, 100, 1000 Mbps Ethernet controllers
(eTSECs), a DDR2 SDRAM memory controller, a SerDes block, an enhanced secure digital host
controller (eSDHC), an enhanced local bus controller (eLBC), an integrated programmable interrupt
controller (IPIC), a general purpose DMA controller, two I
2
C controllers, dual UART (DUART), GPIOs,
USB, general purpose timers, and an SPI controller. The high level of integration in the MPC8308 helps
simplify board design and offers significant bandwidth and performance.
A block diagram of the MPC8308 is shown in Figure 1-1.
Figure 1-1. MPC8308 Block Diagram
The major features of this device are as follows:
• e300c3 processor core
eTSEC1
DUART
Interrupt
I2C
Timers
GPIO, SPI
Enhanced
DDR2
Controller
Controller
Local Bus
PCI
Express
x1
DMA
RGMII,MII
16-KB
D-Cache
16-KB
I-Cache
e300c3 Core with
Power Management
FPU
Enhanced
Secure
Digital Host
Controller
USB 2.0 HS
Host/Device/OTG
ULPI
eTSEC2