Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-69
schedules have not yet been enabled. The EHCI host controller will not transmit SOFs to enabled Full- or
Low-speed ports.
In order to communicate with devices via the asynchronous schedule, system software must write the
ASYNDLISTADDR register with the address of a control or bulk queue head. Software must then enable
the asynchronous schedule by writing a one to USBCMD[ASE]. In order to communicate with devices via
the periodic schedule, system software must enable the periodic schedule by writing a one to
USBCMD[PSE]. Note that the schedules can be turned on before the first port is reset (and enabled).
Any time the USBCMD register is written, system software must ensure the appropriate bits are preserved,
depending on the intended operation.
13.6.2 Power Port
The HCSPARAMS[PPC] bit indicates whether the USB 2.0 host controller has port power control. When
the PPC bit is set, the host controller supports port power switches. Each available switch has an output
enable. PPE is controlled based on the state of the combination bits PPC bit, EHCI Configured (CF)-bit
and individual Port Power (PP) bits.
13.6.3 Reporting Over-Current
Host ports by definition are power providers on USB. Whether the ports are considered high- or
low-powered is a platform implementation issue. The EHCI PORTSC register has an over-current status
and over-current change bit. The functionality of these bits is specified in the USB Specification Revision
2.0.
The over current detection and limiting logic resides outside the DR logic. The over-current condition
effects the following bits in the PORTSC register on the EHCI port:
• Over-current active bit (OCA) is set. When the over-current condition goes away, the OCA will
transition from a one to a zero.
• Over-current change bit (OCC) is set. On every transition of OCA, the controller will set OCC to
a one. Software sets OCC to a zero by writing a one to this bit.
• Port enabled/disabled bit (PE) is cleared. When this change bit gets set, USBSTS[PCI] (the port
change detect bit) is set.
• Port power (PP) bit may optionally be cleared. There is no requirement in USB that a power
provider shut off power in an over current condition. It is sufficient to limit the current and leave
power applied. When OCC transitions from a zero to a one, the controller also sets USBSTS[PCI]
to a one. In addition, if the Port Change Interrupt Enable bit, USBINTR[PCE], is a one, the
controller issues an interrupt to the system. Refer to Table 13-64 for summary of behavior for
over-current detection when the controller is halted (suspended from a device component point of
view).
13.6.4 Suspend/Resume
The host controller provides an equivalent suspend and resume model as that defined for individual ports
in a USB 2.0 hub. Control mechanisms are provided to allow system software to suspend and resume