Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-62 Freescale Semiconductor
13.5.6 Queue Head
Figure 13-41 shows the queue head structure.
13.5.6.1 Queue Head Horizontal Link Pointer
The first DWord of a queue head contains a link pointer to the next data object to be processed after any
required processing in this queue has been completed, as well as the control bits defined below.
This pointer may reference a queue head or one of the isochronous transfer descriptors. It must not
reference a queue element transfer descriptor.
Table 13-57 describes the queue head.
3130292827262524232221201918171615 14131211109 8 76543 2 1 0 offset
Queue Head Horizontal Link Pointer 00 Typ T 0x00
RL C Maximum Packet Length H dtc EPS EndPt I Device Address 0x04
1
1
Offsets 0x04 through 0x0B contain the static endpoint state.
Mult Port Number Hub Addr µFrame C-mask µFrame S-mask 0x08
1
Current qTD Pointer
2
2
Host controller read/write; all others read-only.
00000 0x0C
Next qTD Pointer
2
0000 T
2
0x10
3
3
Offsets 0x10 through 0x2F contain the transfer overlay.
Alternate Next qTD Pointer
2
NakCnt
2
T
2
0x14
3,4
4
Offsets 0x14 through 0x27 contain the transfer results.
dt
1
Total Bytes to Transfer
2
ioc
2
C_Page
2
Cerr
2
PID
Code
2
Status
2
0x18
3,4
Buffer Pointer (Page 0)
2
Current Offset
2
0x1C
3,4
Buffer Pointer (Page 1)
2
0000 C-prog-mask
2
0x20
3,4
Buffer Pointer (Page 2)
2
S-bytes
2
FrameTag
2
0x24
3,4
Buffer Pointer (Page 3)
2
0000_0000_0000 0x28
3
Buffer Pointer (Page 4)
2
0000_0000_0000 0x2C
3
Figure 13-41. Queue Head Layout
Table 13-57. Queue Head DWord 0
Bits Name Description
31–5 QHLP Queue head horizontal link pointer. This field contains the address of the next data object to be processed in
the horizontal list and corresponds to memory address signals [31:5], respectively.
4–3 — Reserved, should be cleared. These bits must be written as zeros.