Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-54 Freescale Semiconductor
13.5.4.3 siTD Transfer State
DWords 3–6 manage the state of the transfer, as described in Table 13-49.
Table 13-49. siTD Transfer Status and Control
Bits Name Description
31 ioc Interrupt on complete
0 Do not interrupt when transaction is complete.
1 Do interrupt when transaction is complete. When the host controller determines that the split
transaction has completed it will assert a hardware interrupt at the next interrupt threshold.
30 P Page select. Indicates which data page pointer should be concatenated with the CurrentOffset field
to construct a data buffer pointer
0 Selects Page 0 pointer
1 Selects Page 1 pointer
The host controller is not required to write this field back when the siTD is retired (Active bit
transitioned from a one to a zero).
29–26 — Reserved, should be cleared. This field reserved for future use and should be cleared.
25–16 Total Bytes to
Transfer
This field is initialized by software to the total number of bytes expected in this transfer. Maximum
value is 1023 (3FFh)
15–8 µFrame
C-prog-mask
Split complete progress mask. This field is used by the host controller to record which split-completes
have been executed.
7–0 Status This field records the status of the transaction executed by the host controller for this slot. This field is
a bit vector with the following encoding:
Status Bits Definition
7 Active. Set by software to enable the execution of an isochronous split transaction
by the host controller.
6 ERR. Set by the host controller when an ERR response is received from the
companion controller.
5 Data buffer error. Set by the host controller during status update to indicate that the
host controller is unable to keep up with the reception of incoming data (overrun) or
is unable to supply data fast enough during transmission (under run). In the case of
an under run, the host controller will transmit an incorrect CRC (thus invalidating
the data at the endpoint). If an overrun condition occurs, no action is necessary.
4 Babble detected. Set by the host controller during status update when” babble” is
detected during the transaction generated by this descriptor.
3 Transaction error (XactErr). Set by the host controller during status update in the
case where the host did not receive a valid response from the device (Time-out,
CRC, Bad PID, etc.). This bit will only be set for IN transactions.
2 Missed microframe. The host controller detected that a host-induced hold- off
caused the host controller to miss a required complete-split transaction.
1 Split transaction state (SplitXstate). The bit encodings are:
0 Do start split. This value directs the host controller to issue a Start split
transaction to the endpoint when a match is encountered in the S-mask.
1 Do complete split. This value directs the host controller to issue a Complete split
transaction to the endpoint when a match is encountered in the C-mask.
0 Reserved, should be cleared. Bit reserved for future use and should be cleared.