Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-53
Table 13-47 describes the endpoint and transaction translator characteristics.
Table 13-41 describes the microframe schedule control.
Table 13-47. Endpoint and Transaction Translator Characteristics
Bits Name Description
31 I/O Direction (I/O). This field encodes whether the full-speed transaction should be an IN or OUT.
0OUT
1IN
30–24 Port Number This field is the port number of the recipient transaction translator.
23 — Reserved, should be cleared. Bit reserved and should be cleared.
22–16 Hub Address This field holds the device address of the companion controllers’ hub.
15–12 — Reserved, should be cleared. Field reserved and should be cleared.
11–8 EndPt Endpoint Number. Selects the particular endpoint number on the device serving as the data source
or sink.
7 — Reserved, should be cleared. Bit is reserved for future use. It should be cleared.
6–0 Device Address Selects the specific device serving as the data source or sink.
Table 13-48. Microframe Schedule Control
Bits Name Description
31–16 — Reserved, should be cleared. This field reserved for future use. It should be cleared.
15–8 µFrame C-mask Split completion mask. This field (along with the Active and SplitX- state fields in the status byte) is
used to determine during which microframes the host controller should execute complete-split
transactions. When the criteria for using this field is met, an all-zeros value has undefined behavior.
The host controller uses the value of the three low-order bits of the FRINDEX register to index into
this bit field. If the FRINDEX register value indexes to a position where the µFrame C-Mask field is
a one, this siTD is a candidate for transaction execution. There may be more than one bit in this
mask set.
7–0 µFrame S-mask Split start mask. This field (along with the Active and SplitX-state fields in the Status byte) is used
to determine during which microframes the host controller should execute start-split transactions.
The host controller uses the value of the three low-order bits of the FRINDEX register to index into
this bit field. If the FRINDEX register value indexes to a position where the µFrame S-mask field is
a one, then this siTD is a candidate for transaction execution. An all zeros value in this field, in
combination with existing periodic frame list has undefined results.