Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-48 Freescale Semiconductor
Figure 13-37. Asynchronous Schedule Organization
The asynchronous list is a simple circular list of queue heads. The ASYNCLISTADDR register is simply
a pointer to the next queue head. This implements a pure round-robin service for all queue heads linked
into the asynchronous list.
13.5.3 Isochronous (High-Speed) Transfer Descriptor (iTD)
Figure 13-38 illustrates the format of an isochronous transfer descriptor. This structure is used only for
high-speed isochronous endpoints. All other transfer types should use queue structures. Isochronous TDs
must be aligned on a 32-byte boundary.
313029282726252423222120191817161514131211109876543210offset
Next Link Pointer 00 Typ T 0x00
Status
1
1
Host controller read/write; all others read-only.
Transaction 0 Length
1
ioc PG
2
Transaction 0 Offset
2
0x04
Status
1
Transaction 1 Length
1
ioc PG
2
Transaction 1 Offset
2
0x08
Status
1
Transaction 2 Length
1
ioc PG
2
Transaction 2 Offset
2
0x0C
Status
1
Transaction 3 Length
1
ioc PG
2
Transaction 3 Offset
2
0x10
Status
1
Transaction 4 Length
1
ioc PG
2
Transaction 4 Offset
2
0x14
Status
1
Transaction 5 Length
1
ioc PG
2
Transaction 5 Offset
2
0x18
Status
1
Transaction 6 Length
1
ioc PG
2
Transaction 6 Offset
2
0x1C
Status
1
Transaction 7 Length
1
ioc PG
2
Transaction 7 Offset
2
0x20
Buffer Pointer (Page 0) EndPt R Device Address 0x24
Buffer Pointer (Page 1) I/O Maximum Packet Size 0x28
Buffer Pointer (Page 2) Reserved Mult 0x2C
Buffer Pointer (Page 3) Reserved 0x30
Buffer Pointer (Page 4) Reserved 0x34
Buffer Pointer (Page 5) Reserved 0x38
Buffer Pointer (Page 6)
Reserved 0x3C
Figure 13-38. Isochronous Transaction Descriptor (iTD)
AsyncListAddr
Operational
Registers
Bulk/Control Queue Heads
H