Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-44 Freescale Semiconductor
13.4 Functional Description
The USB DR module can be broken down into functional sub-blocks, which are described below.
13.4.1 System Interface
The system interface block contains all the control and status registers that allow a processor to interface
to the USB DR module. These registers allow the processor to control the configuration of the module,
ascertain the capabilities of the module, and control the module’s operation. It also has registers to control
snoopability and priority of the DMA interface.
15 WU_INT Reflects the state of the wake up interrupt. The wake up interrupt signal is asserted when a
wake-up event occurs while in a low-power suspend state. If WU_INT_EN is set, this WU_INT
signal generates an interrupt to the system to indicate wake up servicing is required. WU_INT will
remain set until the USB controller is exited from the low power by clearing the PORTSC[PHCD]
bit.
0 Normal operation or Low Power mode waiting for wakeup event
1 Low power wakeup event has occurred
16–20 — Reserved
21 PHY_CLK_SEL Select the source of the USB link controller transceiver clock. When cleared the UTMI PHY is the
source of the clock. When set, the clock is sourced from the external ULPI PHY.
0 UTMI is clock source
1 ULPI is clock source
22–28 — Reserved
29 USB_EN UTMI mode: This bit is used to enable the USB interface. It must be set before setting RS bit in
USB CMD register.
1 Enable
0 Disable
ULPI mode: In safe mode, all USB interface signals are put into input mode or driven inactive,
except for SUSPEND_STP which is driven high. Also, the input signal DIR is forced to appear high
to the controller. This prevents any start-up problems that otherwise could occur if the PHY and
the controller take significantlly different times to complete power-on reset.
1 Normal operation
0 Safe mode
30 WU_INT_EN This bit is used to mask/unmask the system wakeup interrupt signal
0 System wakeup interrupt disabled
1 System wakeup interrupt enabled
Note: PORTSC[PHCD] bit must be set for the system wakeup interrupt generation.
31 ULPI_INT_EN Used to enable the ULPI low power wakeup interrupt from the PHY when the PHY is in low power
mode only.
0 ULPI low power wakeup interrupt disabled
1 ULPI low power wakeup interrupt enabled
Note: PORTSC[PHCD] bit must be set
Table 13-37. CONTROL Field Descriptions (continued)
Bits Name Description