Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-43
Table 13-36 describes the system interface control register fields.
13.3.2.28 USB General Purpose Register (CONTROL)—Non-EHCI
Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The USB
general purpose (CONTROL) register contains the general-purpose IP control register outputs and is
shown in Figure 13-34.
Table 13-37 describes the USB general-purpose register fields.
Table 13-36. SI_CTRL Register Field Descriptions
Bits Name Description
0–26 — Reserved, should be cleared
27 err_disable When this bit is set, it causes the controller to ignore system bus errors. If cleared the controller
responds according to the values set in USBSTS[SEI] and USBINT[SEE].
0 enable
1 disable
28–30 — Reserved, should be cleared
31 rd_prefetch_val Selects whether 32 bytes or 64 bytes are fetched during burst read transactions at the system
interface. When this input is LOW 64 bytes are fetched and when it is HIGH 32 bytes are fetched.
The setting of rd_prefetch_val must match the setting of the larger of TXPBURST and RXPBURST
fields in the BURSTSIZE register. If either of these fields is 64 bytes, then rd_prefetch_val must be
left cleared. Otherwise, this value should be set.
0 64-byte fetch
1 32-byte fetch
Offset 0x500 Access: Read/Write
0 14 15
R
—
PHY_CLK
_VALID
WU_INT
W
Reset All zeros
16 28 29 30 31
R
—
PHY_CLK
_SEL
—
USB_
EN
WU_
INT_EN
ULPI_
INT_EN
W
Reset All zeros
Figure 13-34. USB General-Purpose Register (CONTROL)
Table 13-37. CONTROL Field Descriptions
Bits Name Description
0–13 — Reserved, must be cleared.
14 PHY_CLK_
VALID
Indicates whether the PHY clock is valid (read only). In ULPI mode, this bit reflects the inverted
ULPI DIR. In ULPI mode, this bit is not valid if the USB I/O have not been configured and after the
USB_EN signal is asserted.
0 USB PHY clock is not valid
1 USB PHY clock is valid