Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-42 Freescale Semiconductor
increments of 5. Raising AGE_CNT_THRESH benefits the other controllers on the system bus by
reducing the frequency that this USB controller raises its priority to the arbiter.
13.3.2.26 Priority Control Register (PRI_CTRL)—Non-EHCI
Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The
priority control (PRI_CTRL) register sets the priority level for each of two priority states. The priority state
is determined by the value programmed in the AGE_CNT_THRESH register and the number of csb_clk
cycles that a particular transaction takes to complete.
Figure 13-32 shows the priority control register.
Table 13-35 describes the priority control register fields.
13.3.2.27 System Interface Control Register (SI_CTRL)—Non-EHCI
Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The
system interface control register (SI_CTRL) controls various functions pertaining to the internal system
interface.
Figure 13-33 shows the system interface control register.
Offset 0x40C Access: Read/Write
0 27 28 29 30 31
R
— pri_lvl1 pri_lvl0
W
Reset All zeros
Figure 13-32. Priority Control (PRI_CTRL)
Table 13-35. PRI_CTRL Register Field Descriptions
Bits Name Description
0–27 — Reserved, should be cleared
28–29 pri_lvl1 Priority level for priority state 1.
30–31 pri_lvl0 Priority level for priority state 0.
Offset 0x410 Access: Read/Write
0 26 27 28 30 31
R
—
err_
disable
—
rd_prefetch
_val
W
Reset All zeros
Figure 13-33. System Interface Control Register (SI_CTRL)