Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-39
13.3.2.24 SNOOP1 and SNOOP2—Non-EHCI
Figure 13-30 shows the SNOOP1 and SNOOP2 registers. Note that these registers use big-endian byte
ordering and are not defined in the EHCI specification. The SNOOP1 and SNOOP2 registers provide
snooping control and address range selection function. Transactions that hit a snooping window will
generate cache coherent transactions on the internal CSB bus. When the five lower bits (SNOOPn[27–31])
are equal to 00000, snooping is always disabled on the CSB for all DMA transfers. When SNOOPn[27–31]
is 01011 through 11110, the twenty upper bits (SNOOPn[0–19]) provide the starting base address for
which transactions are snooped. These twenty bits are compared to the twenty upper bits of the address
provided by the DMA block of the USB controller. When a match occurs, the five lower bits are decoded
16 TXS TX endpoint stall. This bit is set automatically upon receipt of a SETUP request if this endpoint is not configured
as a control endpoint. It is cleared automatically upon receipt of a SETUP request if this endpoint is configured
as a control endpoint.
Software can write a one to this bit to force the endpoint to return a STALL handshake to the host. It will continue
to returning STALL until this bit is either cleared by software or automatically cleared as above.
0 Endpoint OK
1 Endpoint stalled
15–8 — Reserved, should be cleared
7 RXE RX endpoint enable
0Disabled
1 Enabled
6 RXR RX data toggle reset. Whenever a configuration event is received for this endpoint, software must write a one to
this bit in order to synchronize the data PID’s between the Host and device.
5 RXI RX data toggle inhibit. This bit is only used for test and should always be written as zero. Writing a one to this
bit will cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of
their data PID.
1 PID sequencing enabled
0 PID sequencing disabled
4 — Reserved, should be cleared
3–2 RXT RX endpoint type
00 Control
01 Isochronous
10 Bulk
11 Interrupt
Note: When only one endpoint (RX or TX, but not both) of an endpoint pair is used, the unused endpoint should
be configured as a bulk type endpoint.
1 RXD RX endpoint data sink. This bit should always be written as 0, which selects the dual port memory/DMA engine
as the sink.
0 RXS RX endpoint stall. This bit is set automatically upon receipt of a SETUP request if this endpoint is not configured
as a control endpoint. It is cleared automatically upon receipt a SETUP request if this endpoint is configured as
a control endpoint,
Software can write a one to this bit to force the endpoint to return a STALL handshake to the host. It will continue
to returning STALL until this bit is either cleared by software or automatically cleared as above,
1 Endpoint stalled
0 Endpoint OK
Table 13-32. ENDPTCTRLn Register Field Descriptions (continued)
Bits Name Description