Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-38 Freescale Semiconductor
13.3.2.23 Endpoint Control Register n (ENDPTCTRLn)—Non-EHCI
The endpoint control n registers, shown in Figure 13-29, are not defined in the EHCI specification. There
is an ENDPTCTRLn register of each endpoint in a device.
Table 13-32 describes the endpoint control n register fields.
1 — Reserved, should be cleared.
0 RXS RX endpoint stall
Software can write a one to this bit to force the endpoint to return a STALL handshake to the host. It will
continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of
a new SETUP request.
1 Endpoint stalled
0 Endpoint OK
Offset 0x1C4 (ENDPTCTRL1), 0x1C8 (ENDPTCTRL2), Access: Read/Write
31 24 23 22 21 20 19 18 17 16 15 8 7 6 5 4 3 2 1 0
R
— TXE TXR TXI — TXT TXD TXS — RXE RXR RXI — RXT RXD RXS
W
Reset All zeros
Figure 13-29. Endpoint Control 1 to 5 (ENDPTCTRLn)
Table 13-32. ENDPTCTRLn Register Field Descriptions
Bits Name Description
31–24 — Reserved, should be cleared
23 TXE TX endpoint enable
0Disabled
1 Enabled
22 TXR TX data toggle reset. Whenever a configuration event is received for this endpoint, software must write a one to
this bit in order to synchronize the data PID’s between the Host and device.
21 TXI TX data toggle inhibit. Used only for test and should always be written as zero. Writing a one to this bit will cause
this endpoint to ignore the data toggle sequence and always transmit DATA0 for a data packet.
0 PID sequencing enabled
1 PID sequencing disabled
20 — Reserved, should be cleared
19–18 TXT TX endpoint type
00 Control
01 Isochronous
10 Bulk
11 Interrupt
Note: When only one endpoint (RX or TX, but not both) of an endpoint pair is used, the unused endpoint should
be configured as a bulk type endpoint.
17 TXD TX endpoint data source. This bit should always be written as 0, which selects the dual port memory/DMA
engine as the source.
Table 13-31. ENDPTCTRL0 Register Field Descriptions (continued)
Bits Name Description