Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-36 Freescale Semiconductor
Table 13-29 describes the endpoint status fields.
13.3.2.21 Endpoint Complete Register (ENDPTCOMPLETE)—Non-EHCI
The endpoint complete register, shown in Figure 13-25, is not defined in the EHCI specification. This
register is only used in device mode.
Table 13-30 describes the endpoint complete register fields.
Table 13-29. ENDPTSTATUS Register Field Descriptions
Bits Name Description
31–19 — Reserved, should be cleared
18–16 ETBR Endpoint transmit buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer. This
bit is set by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME
register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint
indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the
ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the
ENDPTFLUSH register. ETBR[2] (bit 18 of the register) corresponds to endpoint 2.
Note that these bits are momentarily cleared by hardware during hardware endpoint re-priming operations
when a dTD is retired, and the dQH is updated.
15–3 — Reserved, should be cleared
2–0 ERBR Endpoint receive buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer. This
bit is set by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME
register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint
indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the
ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the
ENDPTFLUSH register. ERBR[2] corresponds to endpoint 2.
Note that these bits are momentarily cleared by hardware during hardware endpoint re-priming operations
when a dTD is retired, and the dQH is updated.
Offset 0x1BC Access: w1c
31 21 19 18 16 15 3 2 0
R
—
ETCE
—
ERCE
W w1c w1c
Reset All zeros
Figure 13-27. Endpoint Complete (ENDPTCOMPLETE)
Table 13-30. ENDPTCOMPLETE Register Field Descriptions
Bits Name Description
31–19 — Reserved, should be cleared
18–16 ETCE Endpoint transmit complete event. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software
should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit
is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT. Writing a one will clear the
corresponding bit in this register. ETCE[2] (bit 18 of the register) corresponds to endpoint 2.