Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-35
13.3.2.19 Endpoint Flush Register (ENDPTFLUSH)—Non-EHCI
The endpoint flush register, shown in Figure 13-25, is not defined in the EHCI specification. This register
is only used in device mode.
Table 13-28 describes the endpoint flush register fields.
13.3.2.20 Endpoint Status Register (ENDPTSTATUS)—Non-EHCI
The endpoint status register, shown in Figure 13-25, is not defined in the EHCI specification. This register
is only used in device mode.
Offset 0x1B4 Access: Read/Write
31 19 18 16 15 3 2 0
R
— FETB —FERB
W
Reset All zeros
Figure 13-25. Endpoint Flush (ENDPTFLUSH)
Table 13-28. ENDPTFLUSH Register Field Descriptions
Bits Name Description
31–19 — Reserved, should be cleared.
18–16 FETB Flush endpoint transmit buffer. Writing a one to a bit(s) in this register will cause the associated endpoint(s) to
clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will
continue until completion. Hardware will clear this register after the endpoint flush operation is successful.
FETB[2] (bit 18 of the register) corresponds to endpoint 2.
15–3 — Reserved, should be cleared.
2–0 FERB Flush endpoint receive buffer. Writing a one to a bit(s) will cause the associated endpoint(s) to clear any primed
buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until
completion. Hardware will clear this register after the endpoint flush operation is successful. FERB[2]
corresponds to endpoint 2.
Offset 0x1B8 Access: Read only
31 21 18 16 15 3 2 0
R
—
ETBR
—
ERBR
W
Reset All zeros
Figure 13-26. Endpoint Status (ENDPTSTATUS)