Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-34 Freescale Semiconductor
Table 13-26 describes the endpoint setup status register fields.
13.3.2.18 Endpoint Initialization Register (ENDPTPRIME)—Non-EHCI
The endpoint initialization register, shown in Figure 13-23, is not defined in the EHCI specification. This
register is used to initialize endpoints. It is only used in device mode.
Table 13-27 describes the endpoint initialization register fields.
Table 13-26. ENDPTSETUPSTAT Register Field Descriptions
Bits Name Description
31–3 — Reserved, should be cleared.
2–0 ENDPTSETUP
STAT
Setup endpoint status. For every setup transaction that is received, a corresponding bit in this
register is set. Software must clear or acknowledge the setup transfer by writing a one to a respective
bit after it has read the setup data from queue head. The response to a setup packet as in the order
of operations and total response time is crucial to limit bus time outs while the setup lockout
mechanism is engaged.
This register is only used in device mode.
Offset 0x1B0 Access: Read/Write
31 19 18 16 15 3 2 0
R
— PETB — PERB
W
Reset All zeros
Figure 13-24. Endpoint Initialization (ENDPTPRIME)
Table 13-27. ENDPTPRIME Register Field Descriptions
Bits Name Description
31–19 — Reserved, should be cleared.
18–16 PETB Prime endpoint transmit buffer. For each endpoint a corresponding bit is used to request that a buffer prepared
for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one
to the corresponding bit when posting a new transfer descriptor to an endpoint. Hardware will automatically use
this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer.
Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PETB[2] (bit 18 of the
register) corresponds to endpoint 2.
Note that these bits are momentarily set by hardware during hardware re-priming operations when a dTD is
retired, and the dQH is updated.
15–3 — Reserved, should be cleared.
2–0 PERB Prime endpoint receive buffer. For each endpoint, a corresponding bit is used to request a buffer prepare for a
receive operation in order to respond to a USB OUT transaction. Software should write a one to the
corresponding bit whenever posting a new transfer descriptor to an endpoint. Hardware will automatically use
this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer.
Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed. PERB[2] corresponds
to endpoint 2.
Note that these bits are momentarily set by hardware during hardware re-priming operations when a dTD is
retired, and the dQH is updated.