Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-33
Table 13-25 describes the USB mode register fields.
13.3.2.17 Endpoint Setup Status Register (ENDPTSETUPSTAT)—Non-EHCI
The endpoint setup status register, shown in Figure 13-23, is not defined in the EHCI specification. This
register contains the endpoint setup status. It is only used in device mode.
Table 13-25. USBMODE Register Field Descriptions
Bits Name Description
31–5 — Reserved, should be cleared.
4 SDIS Stream disable
In host mode, setting this bit ensures that overruns/underruns of the latency FIFO are eliminated for low
bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream
disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the
USB.
Note that time duration to pre-fill the FIFO becomes significant when stream disable is active. See
TXFILLTUNING to characterize the adjustments needed for the scheduler when using this feature.
Also note that in systems with high system bus utilization, setting this bit will ensure no overruns or underruns
during operation, at the expense of link utilization. For those who desire optimal link performance, SDIS can be
left clear, and the rules used under the description of the TXFILLTUNING register to limit underruns/overruns.
1Active.
0Inactive.
In device mode, setting this bit disables double priming on both RX and TX for low bandwidth systems. This
mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double
buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems.
Note that in high-speed mode, all packets received are responded to with a NYET handshake when stream
disable is active.
3 SLOM Setup lockout mode. In device mode, this bit controls behavior of the setup lock mechanism. See
Section 13.8.3.5, “Control Endpoint Operation Model.”
1 Setup lockouts off. DCD requires use of setup data buffer tripwire in USBCMD (SUTW).
0 Setup lockouts on
2 — Reserved, should be cleared.
1–0 CM Controller mode
This register can only be written once after reset. If it is necessary to switch modes, software must reset the
controller by writing to USBCMD[RST] before reprogramming this register.
00 Idle (default for combination host/device).
01 Reserved, should be cleared.
10 Device controller (default for device only controller).
11 Host controller (default for host only controller).
Defaults to the idle state and needs to be initialized to the desired operating mode after reset.
Offset 0x1AC Access: Read/Write
31 32 0
R
—
ENDPTSETUP
STAT
W
Reset All zeros
Figure 13-23. Endpoint Setup Status (ENDPTSETUPSTAT)