Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-31
25 AVVIE A VBus valid interrupt enable
1 Enable
0 Disable
24 IDIE USB ID interrupt enable.
1 Enable
0 Disable
23 — Reserved, should be cleared.
22 DPIS Data pulse interrupt status. Set when data bus pulsing occurs on DP or DM. Data bus pulsing is only
detected when USBMODE[CM] = Host (11) and PORTSC[PP] (port power) = Off (0).
Software must write a one to clear this bit.
21 1msS 1-millisecond timer interrupt status. Set once every millisecond.
Software must write a one to clear this bit.
20 BSEIS B session end interrupt status. Set when VBus has fallen below the B session end threshold.
Software must write a one to clear this bit.
19 BSVIS B session valid interrupt status. Set when VBus has either risen above or fallen below the B session valid
threshold (0.8 VDC).
Software must write a one to clear this bit.
18 ASVIS A session valid interrupt status. Set when VBus has either risen above or fallen below the A session valid
threshold (0.8 VDC).
Software must write a one to clear this bit.
17 AVVIS A VBus valid interrupt status. Set when VBus has either risen above or fallen below the VBus valid threshold
(4.4 VDC) on an A device.
Software must write a one to clear this bit.
16 IDIS USB ID interrupt status. Set when a change on the ID input has been detected.
Software must write a one to clear this bit.
15 — Reserved, should be cleared.
14 DPS Data bus pulsing status
1 Pulsing detected on port
0 No pulsing on port
13 1msT 1 millisecond timer toggle. This bit toggles once per millisecond.
12 BSE B session end
1 VBus is below the B session end threshold.
0 VBus is above the B session end threshold.
11 BSV B session valid
1 VBus is above the B session valid threshold.
0 VBus is below the B session valid threshold.
10 ASV A session valid
1 VBus is above the A session valid threshold.
0 VBus is below the A session valid threshold.
9 AVV A VBus valid
1 VBus is above the A VBus valid threshold.
0 VBus is below the A VBus valid threshold.
Table 13-24. OTGSC Register Field Descriptions (continued)
Bits Name Description