Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-27
15–14 PIC Port indicator control. Control the link indicator signals. These signals are valid for host mode only.
00 Off
01 Amber
10 Green
11 Undefined
Refer to the USB Specification Revision 2.0 [3] for a description on how these bits are to be used.
This field is output from the module on the USB port control signals for use by an external LED driving circuit.
13 PO Port owner. Unconditionally goes to a 0 when the configured bit in the CONFIGFLAG register makes a 0 to 1
transition. This bit unconditionally goes to 1 whenever the Configured bit is zero. System software uses this
field to release ownership of the port to a selected the module (in the event that the attached device is not a
high-speed device). Software writes a one to this bit when the attached device is not a high-speed device. A
one in this bit means that an internal companion controller owns and controls the port.
Port owner hand-off is not implemented in this design, therefore this bit is always 0.
12 PP Port power. Represents the current setting of the switch (0=off, 1=on). When power is not available on a port
(that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc.
When an over-current condition is detected on a powered port, the PP bit in each affected port is transitioned
by the host controller driver from a one to a zero (removing power from the port).
This feature is implemented in the host/OTG controller (PPC = 1).
In a device-only implementation port power control is not necessary, thus PPC and PP = 0.
11–10 LS Line status. Reflect the current logical levels of the USB D+ (bit 11) and D– (bit 10) signal lines. The use of line
status by the host controller driver is not necessary (unlike EHCI), because the connection of FS and LS is
managed by hardware.
00 SE0
10 J-state
01 K-state
11 Undefined
9 — Reserved, should be cleared
8 PR Port reset.
Host mode:
• When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision
2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior
is different from EHCI where the host controller driver is required to set this bit to a zero after the reset
duration is timed in the driver.
Device mode:
• This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register.
1 Port is in reset.
0 Port is not in reset.
This field is zero if Port Power(PP) is zero.
Table 13-23. PORTSC Register Field Descriptions (continued)
Bits Name Description