Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-26 Freescale Semiconductor
27–26 PSPD Port speed. This read-only register field indicates the speed at which the port is operating.
This bit is not defined in the EHCI specification.
00 Full-speed
01 Low-speed
10 High-speed
11 Undefined
25 — Reserved, should be cleared
24 PFSC Port force full-speed connect. Used to disable the chirp sequence that allows the port to identify itself as a HS
port. This is useful for testing FS configurations with a HS host, hub or device.
0 Allow the port to identify itself as high speed.
1 Force the port to only connect at full speed.
This bit is not defined in the EHCI specification.
This bit is for debugging purposes.
23 PHCD PHY low power suspend. This bit is not defined in the EHCI specification.
Host mode:
• The PHY can be put into low power suspend – when the downstream device has been put into suspend
mode or when no downstream device is connected. Low power suspend is completely under the control of
software.
Device mode:
• The PHY can be put into low power suspend – when the device is not running (USBCMD[RS] = 0b) or
suspend signaling is detected on the USB. Low power suspend is cleared automatically when the resume
signaling has been detected or when forcing port resume.
0 Normal PHY operation.
1 Signal the PHY to enter low power suspend mode
Reading this bit indicates the status of the PHY.
Note: If there is no clock connected to the USBDR_CLK signals, PHCD must be set and the following registers
should not be written: DEVICE_ADDR/PERIODICLISTBASE, PORTSC, ENDPTCTRL0,
ENDPTCTRL1, ENDPTCTRL2.
22 WKOC Wake on over-current enable. Writing this bit to a one enables the port to be sensitive to over-current conditions
as wake-up events.
This field is zero if Port Power (PP) is zero.
This bit is (OTG/host mode only) for use by an external power control circuit.
21 WKDS Wake on disconnect enable. Writing this bit to a one enables the port to be sensitive to device disconnects as
wake-up events.
This field is zero if Port Power(PP) is zero or in device mode.
This bit is (OTG/host mode only) for use by an external power control circuit.
20 WLCN Wake on connect enable. Writing this bit to a one enables the port to be sensitive to device connects as
wake-up events.
This field is zero if Port Power(PP) is zero or in device mode.
This bit is (OTG/host mode only) for use by an external power control circuit.
19–16 PTC Port test control. Any other value than zero indicates that the port is operating in test mode.
0000 Not Enabled
0001 J_STATE
0010 K_STATE
0011 SEQ_NAK
0100 Packet
0101 FORCE_ENABLE
0110–1111 Reserved, should be cleared
Refer to Chapter 7 of the USB Specification Revision 2.0 [3] for details on each test mode.
Table 13-23. PORTSC Register Field Descriptions (continued)
Bits Name Description