Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-25
Table 13-22 describes the configure flag register fields.
13.3.2.14 Port Status and Control Register (PORTSC)
The port status and control (PORTSC) register, shown in Figure 13-20, is only reset when power is initially
applied or in response to a controller reset. The initial conditions of a port are:
• No device connected
• Port disabled
If the port has port power control, this state remains until software applies power to the port by setting port
power to one.
In device mode, the USB DR controller does not support power control. Port control in device mode is
only used for status port reset, suspend, and current connect status. It is also used to initiate test mode or
force signaling and allows software to put the PHY into low power suspend mode and disable the PHY
clock.
Table 13-23 describes the PORTSC register fields.
Table 13-22. CONFIGFLAG Register Field Descriptions
Bits Name Description
31–1 — Reserved.
0 CF Configure flag. Always 1 indicating all port routings default to this host.
Offset 0x184 Access: Mixed
31 30 29 28 27 26 25 24 23 22 21 20 19 16
R
PTS — —
PSPD
— PFSC PHCD WKOC WKDS WLCN PTC
W
Reset000100000 0 0 00000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
PIC PO PP
LS
—PRSUSPFPR
OCC OCA PEC
PE
CSC CCS
W
w1c w1c w1c
Reset000000000 0 0 00000
Figure 13-20. Port Status and Control (PORTSC)
Table 13-23. PORTSC Register Field Descriptions
Bits Name Description
31–30 PTS Port transceiver select. This register bit is used to control which parallel transceiver interface is selected.
00 Reserved
01 Reserved
10 ULPI parallel interface
11 Reserved
This bit is not defined in the EHCI specification.
29 — Reserved, should be cleared
28 — Reserved