Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
vi Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
5.7.1 External Signal Description....................................................................................... 5-70
5.7.2 PMC Memory Map/Register Definition.................................................................... 5-70
5.7.3 Functional Description............................................................................................... 5-71
Chapter 6
Arbiter and Bus Monitor
6.1 Overview.......................................................................................................................... 6-1
6.1.1 Coherent System Bus Overview.................................................................................. 6-1
6.2 Arbiter Memory Map/Register Definition....................................................................... 6-2
6.2.1 Arbiter Configuration Register (ACR) ........................................................................ 6-3
6.2.2 Arbiter Timers Register (ATR) .................................................................................... 6-4
6.2.3 Arbiter Event Enable Register (AEER)....................................................................... 6-5
6.2.4 Arbiter Event Register (AER)...................................................................................... 6-6
6.2.5 Arbiter Interrupt Definition Register (AIDR).............................................................. 6-7
6.2.6 Arbiter Mask Register (AMR)..................................................................................... 6-8
6.2.7 Arbiter Event Attributes Register (AEATR)................................................................ 6-9
6.2.8 Arbiter Event Address Register (AEADR)................................................................ 6-10
6.2.9 Arbiter Event Response Register (AERR)................................................................. 6-11
6.3 Functional Description................................................................................................... 6-12
6.3.1 Arbitration Policy ...................................................................................................... 6-12
6.3.2 Bus Error Detection ................................................................................................... 6-15
6.4 Initialization/Applications Information ......................................................................... 6-18
6.4.1 Initialization Sequence............................................................................................... 6-18
6.4.2 Error Handling Sequence........................................................................................... 6-18
Chapter 7
e300 Processor Core Overview
7.1 Overview.......................................................................................................................... 7-1
7.1.1 Features........................................................................................................................ 7-3
7.1.2 Instruction Unit............................................................................................................ 7-6
7.1.3 Independent Execution Units....................................................................................... 7-7
7.1.4 Completion Unit .......................................................................................................... 7-8
7.1.5 Memory Subsystem Support........................................................................................ 7-8
7.1.6 Bus Interface Unit (BIU) ........................................................................................... 7-10
7.1.7 System Support Functions ......................................................................................... 7-11
7.2 e300 Processor and System Version Numbers............................................................... 7-13
7.3 PowerPC Architecture Implementation......................................................................... 7-13
7.4 Implementation-Specific Information............................................................................ 7-14
7.4.1 Register Model........................................................................................................... 7-14