Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-21
Table 13-19 describes the master interface data burst size register fields.
13.3.2.11 Transmit FIFO Tuning Controls Register (TXFILLTUNING)—Non-EHCI
The transmit FIFO tuning controls register, shown in Figure 13-17, is not defined in the EHCI
specification. This register is used to control and dynamically change the burst size used during data
movement on device DMA transfers. It is only used in host mode.
The fields in this register control performance tuning associated with how the USB DR module posts data
to the TX latency FIFO before moving the data onto the USB bus. The specific areas of performance
include the how much data to post into the FIFO and an estimate for how long that operation should take
in the target system.
Definitions:
T0 = Standard packet overhead
T1 = Time to send data payload
Ts = Total Packet Flight Time (send-only) packet (Ts = T0 + T1)
Tff = Time to fetch packet into TX FIFO up to specified level.
Tp = Total Packet Time (fetch and send) packet (Tp = Tff + Ts)
Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller checks to ensure
Tp remains before the end of the [micro]frame. If so it proceeds to pre-fill the TX FIFO. If at any time
during the pre-fill operation the time remaining the [micro]frame is < Ts then the packet attempt ceases
and the packet is tried at a later time. Although this is not an error condition and the module eventually
recovers, a mark is made in the scheduler health counter to note the occurrence of a back-off event. When
a back-off event is detected, the partial packet fetched may need to be discarded from the latency buffer to
make room for periodic traffic that will begin after the next SOF. Too many back-off events can waste
Offset 0x160 Access: Read/Write
31 16 15 8 7 0
R
— TXPBURST RXPBURST
W
Reset00000000000000000001000000010000
Figure 13-16. Master Interface Data Burst Size (BURSTSIZE)
Table 13-19. BURSTSIZE Register Field Descriptions
Bits Name Description
31–16 — Reserved, should be cleared.
15–8 TXPBURST Programmable TX burst length. This register represents the maximum length of a burst in 32-bit words
while moving data from system memory to the USB bus. Must not be set to greater that 16.
7–0 RXPBURST Programmable RX burst length. This register represents the maximum length of a burst in 32-bit words
while moving data from the USB bus to system memory. Must not be set to greater than 16.