Information

Universal Serial Bus Interface

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

13-20 Freescale Semiconductor

Table 13-17 describes the current asynchronous list address register.

13.3.2.9 Endpoint List Address Register (ENDPOINTLISTADDR)—Non-EHCI

The endpoint list address register is not defined in the EHCI specification. In device mode, this register

contains the address of the top of the endpoint list in system memory. Bits 10–0 of this register cannot be

modified by the system software and always return zeros when read. The memory structure referenced by

this physical memory pointer is assumed to be 64-bytes. The queue head is actually a 48-byte structure,

but must be aligned on 64-byte boundary. However, the ENDPOINTLISTADDR[EPBASE] has a

granularity of 2 Kbytes, so in practice the queue head should be 2-Kbyte aligned.

Note that this register is shared between the host and device mode functions. In device mode, it is the

ENDPOINTLISTADDR register; in host mode, it is the ASYNCLISTADDR register. See

Section 13.3.2.8, “Current Asynchronous List Address Register (ASYNCLISTADDR),” for more

information.

Figure 13-15 shows the endpoint list address register.

Table 13-18 describes the endpoint list address register fields.

13.3.2.10 Master Interface Data Burst Size Register (BURSTSIZE)—Non-EHCI

The master interface data burst size register, shown in Figure 13-16, is not defined in the EHCI

specification. This register is used to control and dynamically change the burst size used during data

movement on the initiator (master) interface.

Table 13-17. ASYNCLISTADDR Register Field Descriptions

Bits Name Description

31–5 ASYBASE Link pointer low (LPL). These bits correspond to memory address signals [31:5]. This field may only

reference a queue head (QH). Only used by the host controller.

4–0 — Reserved, should be cleared.

Offset 0x158 Access: Read/Write

31 11 10 0

EPBASE —

Reset All zeros

Figure 13-15. Endpoint List Address (ENDPOINTLISTADDR)

Table 13-18. ENDPOINTLISTADDR Register Field Descriptions

Bits Name Description

31–11 EPBASE Endpoint list address. Address of the top of the endpoint list.

10–0 — Reserved, should be cleared.