Information

Universal Serial Bus Interface

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 13-19

Note that this register is shared between the host and device mode functions. In device mode, it is the

DEVICEADDR register; in host mode, it is the PERIODICLISTBASE register. See Section 13.3.2.6,

“Periodic Frame List Base Address Register (PERIODICLISTBASE),” for more information.

Figure 13-12 shows the device address register.

Table 13-16 shows the device address register field descriptions.

13.3.2.8 Current Asynchronous List Address Register (ASYNCLISTADDR)

This 32-bit register contains the address of the next asynchronous queue head to be executed by the host.

Bits 4–0 of this register cannot be modified by the system software and always return zeros when read.

Note that this register is shared between the host and device mode functions. In host mode, it is the

ASYNCLISTADDR register; in device mode, it is the ENDPOINTLISTADDR register. See

Section 13.3.2.9, “Endpoint List Address Register (ENDPOINTLISTADDR)—Non-EHCI,” for more

information.

Figure 13-14 shows the current asynchronous list address register.

Offset 0x154 Access: Read/Write

31 25 24 0

USBADR —

Reset All zeros

Figure 13-13. Device Address (DEVICEADDR)

Table 13-16. DEVICEADDR Register Field Descriptions

Bits Name Description

31–25 USBADR Device address. This field corresponds to the USB device address.

24–0 — Reserved, should be cleared.

Offset 0x158 Access: Read/Write

31 54 0

ASYBASE —

Reset All zeros

Figure 13-14. Current Asynchronous List Address (ASYNCLISTADDR)