Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-16 Freescale Semiconductor
13.3.2.4 Frame Index Register (FRINDEX)
In host mode, the frame index register is used by the controller to index the periodic frame list. The register
updates every 125 microseconds (once each microframe). Bits N–3 are used to select a particular entry in
the periodic frame list during periodic schedule execution. The number of bits used for the index depends
on the size of the frame list as set by system software in USBCMD[FS].
8 SLE Sleep enable. This is a non-EHCI bit. When this bit is a one, and USBSTS[SLI] transitions, the USB DR
controller issues an interrupt. The interrupt is acknowledged by software writing a one to USBSTS[SLI].
Only used in device mode.
0 Disable
1 Enable
7 SRE SOF received enable. This is a non-EHCI bit. When this bit is a one, and USBSTS[SRI] is a one, the
controller issues an interrupt. The interrupt is acknowledged by software clearing USBSTS[SRI].
0 Disable
1 Enable
6 URE USB reset enable. This is a non-EHCI bit. When this bit is a one, USBSTS[URI] is a one, the device
controller issues an interrupt. The interrupt is acknowledged by software clearing USBSTS[URI] bit. Only
used in device mode.
0 Disable
1 Enable
5 AAE Interrupt on async advance enable. When this bit is a one, and USBSTS[AAI] is a one, the controller issues
an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing
USBSTS[AAI]. Only used in host mode.
0 Disable
1 Enable
4 SEE System error enable. When this bit is a one, and USBSTS[SEI] is a one, the controller issues an interrupt.
The interrupt is acknowledged by software clearing USBSTS[SEI].
0 Disable
1 Enable
3 FRE Frame list rollover enable. When this bit is a one, and USBSTS[FRI] is a one, the controller issues an
interrupt. The interrupt is acknowledged by software clearing USBSTS[FRI]. Only used by the host mode.
0 Disable
1 Enable
2 PCE Port change detect enable. When this bit is a one, and USBSTS[PCI] is a one, the controller issues an
interrupt. The interrupt is acknowledged by software clearing USBSTS[PCI].
0 Disable
1 Enable
1 UEE USB error interrupt enable. When this bit is a one, and USBSTS[UEI] is a one, the controller issues an
interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing USBSTS[UEI].
0 Disable
1 Enable
0 UE USB interrupt enable. When this bit is a one, and USBSTS[UI] is a one, the DR controller issues an interrupt
at the next interrupt threshold. The interrupt is acknowledged by software clearing USBSTS[UI].
0 Disable
1 Enable
Table 13-12. USBINTR Register Field Descriptions (continued)
Bits Name Description