Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-15
13.3.2.3 USB Interrupt Enable Register (USBINTR)
The interrupts to software are enabled with the USB interrupt enable register, shown in Figure 13-10. An
interrupt is generated when a bit is set and the corresponding interrupt is active. The USB status register
(USBSTS) still shows interrupt sources even if they are disabled by the USBINTR register, allowing
polling of interrupt events by the software.
Table 13-12 shows the USBINTR register field descriptions.
1UEI
(USBERRINT)
USB error interrupt (USBERRINT). When completion of a USB transaction results in an error
condition, this bit is set by the controller. This bit is set along with the UI, if the TD on which the error
interrupt occurred also had its interrupt on complete (IOC) bit set. See Section 4.15.1 in EHCI for a
complete list of host error interrupt conditions. Also see Table 13-91 in this chapter for more
information on device error matrix. For the USB DR controller in device mode, only resume signaling
is detected, all others are ignored.
0 No error
1 Error detected
0UI
(USBINT)
USB interrupt (USBINT). This bit is set by the controller when the cause of an interrupt is a completion
of a USB transaction where the transfer descriptor (TD) has an interrupt on complete (IOC) bit set.
This bit is also set by the controller when a short packet is detected. A short packet is when the actual
number of bytes received was less than the expected number of bytes.
Offset 0x148 Access: Read/Write
31 16
R
—
W
Reset All zeros
15 11109876543210
R
— ULPIE — SLE SRE URE AAE SEE FRE PCE UEE UE
W
Reset All zeros
Figure 13-10. USB Interrupt Enable (USBINTR)
Table 13-12. USBINTR Register Field Descriptions
Bits Name Description
31–11 — Reserved, should be cleared.
10 ULPIE ULPI interrupt enable. An event completion to the viewport register sets the USBSTS[ULPII]. If the ULPI
enables ULPIE bit to be set, then the USBINT (USBSTS[UI]) occurs.
0 Disable
1 Enable
9 — Reserved, should be cleared.
Table 13-11. USBSTS Register Field Descriptions (continued)
Bits Name Description