Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-14 Freescale Semiconductor
8 SLI DCSuspend. This is a non-EHCI bit. When a device controller enters a suspend state from an active
state, this bit is set. The device controller clears the bit upon exiting from a suspend state. Only used
by the device controller.
0 Active
1 Suspended
7 SRI Host mode:
• This is a non-EHCI status bit. In host mode, this bit is set every 125 us, provided the PHY clock is
present and running (for example, the port is NOT suspended), and can be used by the host
controller driver as a time base.
Device mode:
• SOF received. When the USB DR controller detects a Start Of (Micro)Frame, this bit is set. When
a SOF is extremely late, the DR controller automatically sets this bit to indicate that an SOF was
expected. Therefore, this bit is set roughly every 1 msec in device FS mode and every 125 msec
in HS mode and is synchronized to the actual SOF that is received. Because the controller is
initialized to FS before connect, this bit is set at an interval of 1 msec during the prelude to the
connect and chirp.
Software writes a 1 to this bit to clear it.
6 URI USB reset received. This is a non-EHCI bit. When the USB DR controller detects a USB reset and
enters the default state, this bit is set. Software can write a 1 to this bit to clear the USB reset received
status bit. Only used by the device mode.
0 No reset received
1 Reset received
5 AAI Interrupt on async advance. System software can force the controller to issue an interrupt the next
time the USB DR controller advances the asynchronous schedule by writing a one to USBCMD[IAA].
This status bit indicates the assertion of that interrupt source. Only used by the host mode.
0 No async advance interrupt
1 Async advance interrupt
4 SEI System error. This bit is set whenever an error is detected on the system bus. If USBINTR[SEE] is set,
an interrupt is generated. The interrupt and status bits remain asserted until cleared by writing a 1 to
this bit. Additionally, when in host mode, USBCMD[RS] is cleared, effectively disabling the USB DR
controller. For the USB DR controller in device mode, an interrupt is generated, but no other action is
taken.
0 Normal operation
1 Error
3 FRI Frame list rollover. The controller sets this bit to a one when the frame list index rolls over from its
maximum value to zero. The exact value at which the rollover occurs depends on the frame list size.
For example. If the frame list size (as programmed in USBCMD[FS]) is 1024, FRINDEX rolls over
every time FRINDEX [1 3] toggles. Similarly, if the size is 512, the USB DR controller sets this bit to a
one every time FHINDEX [12] toggles. Only used by the host mode.
2 PCI Host mode:
• Port change detect. The controller sets this bit when a connect status occurs on any port, a port
enable/disable change occurs, an over current change occurs, or PORTSC[FPR] is set as the result
of a J-K transition on the suspended port.
Device mode:
• The USB DR controller sets this bit when it enters the full or high-speed operational state. When
the it exits the full or high-speed operation states due to reset or suspend events, the notification
mechanisms are USBSTS[URI] and USBSTS[SLI], respectively.
This bit is not EHCI compatible.
Table 13-11. USBSTS Register Field Descriptions (continued)
Bits Name Description