Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-13
13.3.2.2 USB Status Register (USBSTS)
Figure 13-9 shows the USB status register, which indicates various states of the USB DR module and any
pending interrupts. This register does not indicate status resulting from a transaction on the serial bus.
Software clears certain bits in this register by writing a 1 to them (indicated by a w1c in the bit’s W cell).
Table 13-11 shows the USBSTS register field descriptions.
Offset 0x144 Access: Mixed
31 16
R
—
W
Reset All zeros
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R AS PS RCL HCH
—
ULPII
—
SLI SRI URI AAI SEI FRI PCI UEI UI
W
w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset All zeros
Figure 13-9. USB Status Register (USBSTS)
Table 13-11. USBSTS Register Field Descriptions
Bits Name Description
31–16 — Reserved, should be cleared.
15 AS Asynchronous schedule status. Reports the current real status of the asynchronous schedule. The
USB DR controller is not required to immediately disable or enable the asynchronous schedule when
software transitions USBCMD[ASE]. When this bit and USBCMD[ASE] have the same value, the
asynchronous schedule is either enabled (1) or disabled (0). Only used in host mode.
0 Disabled
1 Enabled
14 PS Periodic schedule status. Reports the current real status of the periodic schedule. The USB DR
controller is not required to immediately disable or enable the periodic schedule when software
transitions USBCMD[PSE]. When this bit and USBCMD[PSE] have the same value, the periodic
schedule
is either enabled (1) or disabled (0). Only used in host mode.
0 Disabled
1 Enabled
13 RCL Reclamation. Used to detect an empty asynchronous schedule. Only used by the host mode.
0 Non-empty asynchronous schedule
1 Empty asynchronous schedule
12 HCH HC haIted. This bit is a zero whenever USBCMD[RS] is a one. The USB DR controller sets this bit to
one after it has stopped executing because of USBCMD[RS] being cleared, either by software or by
the host controller hardware (for example, internal error). Only used in host mode.
0 Running
1Halted
11 — Reserved, should be cleared.
10 ULPII ULPI interrupt. An event completion to the viewport register sets this bit. If the ULPI enables the
USBINTR[ULPIE] to be set, the USB interrupt (UI) occurs.
9 — Reserved, should be cleared.