Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-12 Freescale Semiconductor
5 ASE Asynchronous schedule enable. Controls whether the controller skips processing the asynchronous
schedule. Only used in host mode.
0 Do not process the asynchronous schedule
1 Use the ASYNCLISTADDR register to access the asynchronous schedule.
4 PSE Periodic schedule enable. Controls whether the controller skips processing the periodic schedule. Only
used in host mode.
0 Do not process the periodic schedule.
1 Use the PERIODICLISTBASE register to access the periodic schedule.
3–2 FS Frame list size. Together with bit 15 these bits make the FS[2:0] field. This field is read/write only if
programmable frame list flag in the HCCPARAMS registers is set to 1. This field specifies the size of the
frame list that controls which bits in FRINDEX should be used for the frame list current index. Only used in
host mode. Note that values below 256 elements are not defined in the EHCI specification.
000 1024 elements (4096 bytes)
001 512 elements (2048 bytes)
010 256 elements (1024 bytes)
011 128 elements (512 bytes)
100 64 elements (256 bytes)
101 32 elements (128 bytes)
110 16 elements (64 bytes)
111 8 elements (32 bytes)
1 RST Controller reset. Software uses this bit to reset the controller. This bit is cleared by the controller when the
reset process is complete. Software cannot terminate the reset process early by writing a zero to this
register.
Host mode:
• When software sets this bit, the host controller resets its internal pipelines, timers, counters, state
machines etc. to their initial value. Any transaction currently in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports. Software should not set this bit when
USBSTS[HCH] is a zero. Attempting to reset an actively running host controller results in undefined
behavior.
Device mode:
• When software sets this bit, the USB DR controller resets its internal pipelines, timers, counters, state
machines etc. to their initial value. Any transaction currently in progress on USB is immediately
terminated. Writing a one to this bit in device mode is not recommended.
0RSRun/Stop.
Host mode:
• When this bit is set, the controller proceeds with the execution of the schedule. The controller continues
execution as long as this bit is set. When this bit is set to 0, the host controller completes the current
transaction on the USB and then halts. The USBSTS[HCH] bit indicates when the USB DR controller has
finished the transaction and has entered the stopped state. Software should not write a one to this field
unless the controller is in the halted state (that is, USBSTS[HCH] is a one).
Device mode:
• Setting this bit causes the USB DR controller to enable a pull-up on D+ and initiate an attach event. This
control bit is not directly connected to the pull-up enable, as the pull-up is disabled upon transitioning into
high-speed mode. Software should use this bit to prevent an attach event before the controller has been
properly initialized. Clearing this bit causes a detach event.
0Stop
1 Run
Table 13-10. USBCMD Register Field Descriptions (continued)
Bits Name Description