Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-11
Table 13-10 provides bit descriptions for the USBCMD register.
Table 13-10. USBCMD Register Field Descriptions
Bits Name Description
31–24 — Reserved, should be cleared.
23–16 ITC Interrupt threshold control. The system software uses this field to set the maximum rate at which the USB
DR module issues interrupts. ITC contains the maximum interrupt interval measured in microframes. Valid
values are shown below.
0x00 Immediate (no threshold)
0x01 1 microframe
0x02 2 microframes
0x04 4 microframes
0x08 8 microframes
0x10 16 microframes
0x20 32 microframes
0x40 40 microframes
15 FS2 See bits 3–2 below. This is a non-EHCI bit.
14 ATDTW Add dTD TripWire. This is a non-EHCI bit. Used as a semaphore when a dTD is added to an active (primed)
endpoint. This bit is set and cleared by software. This bit shall also be cleared by hardware when is state
machine is hazard region where adding a dTD to a primed endpoint may go unrecognized. More information
on the use of this bit is described in Section 13.9.2, “Device Operation.”
13 SUTW Setup tripwire. This is a non-EHCI bit. Used as a semaphore when the 8 bytes of setup data read extracted
from a QH by the DCD. If the setup lockout mode is off (See USBMODE) then there exists a hazard when
new setup data arrives and the DCD is copying setup from the QH for a previous setup packet. This bit is
set and cleared by software and will be cleared by hardware when a hazard exists. More information on the
use of this bit is described in Section 13.9.2, “Device Operation.”
12 — Reserved, should be cleared.
11 ASPE Asynchronous schedule park mode enable. Software uses this bit to enable or disable park mode.
0 Disabled
1 Enabled
10 — Reserved, should be cleared.
9–8 ASP Asynchronous schedule park mode count. This field defaults to 0x3 and is R/W. It contains a count of the
number of successive transactions the host controller is allowed to execute from a high-speed queue head
on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are
0x1H to 0x3H. Software must not write a zero to this field when ASPE is set as this results in undefined
behavior.
7 LR Light host/device controller reset (OPTIONAL). Not implemented. Always 0.
6 IAA Interrupt on async advance doorbell. Used as a doorbell by software to tell the USB DR controller to issue
an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the
doorbell.
When the controller has evicted all appropriate cached schedule states, it sets USBSTS[AAI]. If
USBINTR[AAE] is set, the host controller asserts an interrupt at the next interrupt threshold.
The controller clears this bit after it has set USBSTS[AAI]. Software should not set this bit when the
asynchronous schedule is inactive. Doing so yields undefined results.
This bit is only used in host mode. Setting this bit when the USB DR module is in device mode is selected
results in undefined results.