Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-10 Freescale Semiconductor
13.3.1.6 Device Controller Capability Parameters (DCCPARAMS)—Non-EHCI
This register is not defined in the EHCI specification. This register describes the overall host/device
capability of the DR module. Figure 13-7 shows the DCCPARAMS register.
Table 13-9 provides bit descriptions for the DCCPARAMS register.
13.3.2 Operational Registers
The operational registers are comprised of dynamic control or status registers that may be read-only,
read/write, or read/write-1-to-clear. The following sections define the operational registers.
13.3.2.1 USB Command Register (USBCMD)
Figure 13-8 shows the USB command register. The module executes the command indicated in this
register.
Offset 0x124 Access: Read-only
31 98 765 4 0
R
—
HC DC
—
DEN
W
Reset0000000000000000000000 1 1 00 0 0 0 1 1
Figure 13-7. Device Control Capability Parameters (DCCPARAMS)
Table 13-9. DCCPARAMS Register Field Descriptions
Bits Name Description
31–9 — Reserved, should be cleared.
8 HC Host capable. Always 1, indicating the USB DR controller can operate as an EHCI compatible USB 2.0 host
7 DC Device capable. Always 1, indicating the USB DR controller can operate as an USB 2.0 device.
1 Device capability.
0 No device capability (host only).
6–5 — Reserved, should be cleared.
4–0 DEN Device endpoint number. Indicates the number of endpoints built into the device controller. Always 0x3.
Offset 0x140 Access: Mixed
31 24 23 16
R
—
ITC
W
Reset0 0 00000000001000
1514131211109876543210
R
FS2 ATDTW SUTW — ASPE — ASP
LR
IAA ASE PSE FS1 FS0 RST RS
W
Reset0 0 00000000000000
Figure 13-8. USB Command Register (USBCMD)