Information

Universal Serial Bus Interface

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1

Freescale Semiconductor 13-9

13.3.1.5 Device Controller Interface Version (DCIVERSION)—Non-EHCI

This register is not defined in the EHCI specification. DCIVERSION is a two-byte register containing a

BCD encoding of the device controller interface. The most-significant byte of the register represents a

major revision and the least-significant byte is the minor revision. Figure 13-6 shows the DCIVERSION

Table 13-8 provides bit descriptions for the DCIVERSION register.

2 ASP Asynchronous schedule park capability. Indicates whether the USB DR module supports the park feature

for high-speed queue heads in the asynchronous schedule. The feature can be disabled or enabled and set

to a specific level using the asynchronous schedule park mode enable and asynchronous schedule park

mode count fields in the USBCMD register.

This field is always 1 (park feature supported).

1 PFL Programmable frame list flag. Indicates whether system software can specify and use a frame list length

less that 1024 elements. Frame list size is configured via the USBCMD register frame list size field. The

frame list must always be aligned on a 4-K page boundary. This requirement ensures that the frame list is

always physically contiguous.

This field is always 1.

0 ADC 64-bit addressing capability. Always 0; 64-bit addressing is not supported.

0 Data structures use 32-bit address memory pointers

Offset 0x120 Access: Read-only

15 0

R DCIVERSION

Reset0000000000000001

Figure 13-6. Device Interface Version (DCIVERSION)

Table 13-8. DCIVERSION Register Field Descriptions

Bits Name Description

15–0 DCIVERSION Device interface revision number.

Table 13-7. HCCPARAMS Register Field Descriptions (continued)

Bits Name Description