Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-8 Freescale Semiconductor
13.3.1.4 Host Controller Capability Parameters (HCCPARAMS)
HCCPARAMS identifies multiple mode control (time-base bit functionality) addressing capability.
Figure 13-5 shows the HCCPARAMS register.
Table 13-7 provides bit descriptions for the HCCPARAMS register.
23–20 N_PTT Ports per transaction translator. This is a non-EHCI field. The number of ports assigned to each
transaction translator. This is equal to N_PORTS.
19–17 — Reserved, should be cleared.
16 PI Port indicators. Indicates whether the ports support port indicator control. Always 1.
1 The port status and control registers include a R/W field for controlling the state of the port indicator.
15–12 N_CC Number of companion controllers associated with the DR controller. Always 0.
11–8 N_PCC Number ports per CC. This field indicates the number of ports supported per internal companion
controller. Always 0.
7–5 — Reserved, should be cleared.
4 PPC Power port control. Indicates whether the host controller supports port power control. Always 1.
1 Ports have power port switches.
3–0 N_PORTS Number of ports. Number of physical downstream ports implemented for host applications. The value
of this field determines how many port registers are addressable in the operational register. Always 1.
Offset 0x108 Access: Read-only
31 16 15 8 7 4 3 2 1 0
R
—
EECP IST
—
ASP PFL ADC
W
Reset000000000000000000000000000 0 0 1 1 0
Figure 13-5. Host Control Capability Parameters (HCCPARAMS)
Table 13-7. HCCPARAMS Register Field Descriptions
Bits Name Description
31–16 — Reserved, should be cleared.
15–8 EECP EHCI extended capabilities pointer. Indicates the existence of a capabilities list. A value of 0x00 indicates
no extended capabilities are implemented. A non-zero value in this register indicates the offset in PCI
configuration space of the first EHCI extended capability. The pointer value must be 0x40 or greater if
implemented to maintain the consistency of the PCI header defined for this class of device.
This field is always 0.
7–4 IST Isochronous scheduling threshold. Indicates, relative to the current position of the executing host controller,
where software can reliably update the isochronous schedule. When bit 7 is zero, the value of the least
significant 3 bits indicates the number of microframes a host controller can hold a set of isochronous data
structures (one or more) before flushing the state. When bit 7 is a one, then host software assumes the host
controller may cache an isochronous data structure for an entire frame.
This field is always 0.
3 — Reserved, should be cleared.
Table 13-6. HCSPARAMS Register Field Descriptions (continued)
Bits Name Description