Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-7
Table 13-4 provides bit descriptions for the CAPLENGTH register.
13.3.1.2 Host Controller Interface Version (HCIVERSION)
HCIVERSION contains a BCD encoding of the EHCI revision number supported by this host controller.
The most-significant byte of the register represents a major revision and the least-significant byte is the
minor revision. Figure 13-3 shows the HCIVERSION register.
Table 13-5 provides bit descriptions for the HCIVERSION register.
13.3.1.3 Host Controller Structural Parameters (HCSPARAMS)
HCSPARAMS contains structural parameters such as the number of downstream ports. Figure 13-4 shows
the HCSPARAMS register.
Table 13-6 provides bit descriptions for the HCSPARAMS register.
Table 13-4. CAPLENGTH Register Field Descriptions
Bits Name Description
7–0 CAPLENGTH Capability registers length. Value is 0x40.
Offset 0x102 Access: Read-only
15 0
R HCIVERSION
W
Reset0000000100000000
Figure 13-3. Host Controller Interface Version (HCIVERSION)
Table 13-5. HCIVERSION Register Field Descriptions
Bits Name Description
15–0 — EHCI revision number. Value is 0x0100 indicating version 1.0.
Offset 0x104 Access: Read-only
31 28 27 24 23 20 19 17 16 15 12 11 8 7 5 4 3 0
R
—
N_TT N_PTT
—
PI N_CC N_PCC
—
PPC N_PORTS
W
Reset000000000000000100000000000 1 000 1
Figure 13-4. Host Controller Structural Parameters (HCSPARAMS)
Table 13-6. HCSPARAMS Register Field Descriptions
Bits Name Description
31–28 — Reserved, should be cleared.
27–24 N_TT Number of transaction translators. This is a non-EHCI field. This field indicates the number of embedded
transaction translators associated the module. Always 1. See Section 13.9.1, “Embedded Transaction
Translator Function.”