Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-6 Freescale Semiconductor
The following sections provide details about the registers in the USB memory map.
NOTE
Memory may be viewed from either a big-endian or little-endian byte
ordering perspective depending on the processor configuration. In
big-endian mode, the most-significant byte of word 0 is located at address 0
and the least-significant byte of word 0 is located at address 3. In
little-endian mode, the least-significant byte of word 0 is located at address
0 and the most-significant byte of word 0 is located at address 3. Within
registers, bits are numbered within a word starting with bit 31 as the
most-significant bit. By convention USB registers use little-endian byte
ordering. In the USB DR module, these are the registers from offsets 0x00
to 0x1FF. The registers associated with the internal system interface (0x400
and above) use big-endian byte ordering.
13.3.1 Capability Registers
The capability registers specify the software limits, restrictions, and capabilities of the host/device
controller implementation. Most of these registers are defined by the EHCI specification. Registers that
are not defined by the EHCI specification are noted in their descriptions.
13.3.1.1 Capability Registers Length (CAPLENGTH)
CAPLENGTH is used as an offset to add to the register base address to find the beginning of the
operational register space, that is, the location of the USBCMD register. Figure 13-2 shows
CAPLENGTH.
0x40C PRI_CTRL—Priority control R/W 0x0000_0000 13.3.2.26/13-42
0x410 SI_CTRL—System interface control R/W 0x0000_0000 13.3.2.27/13-42
0x500 CONTROL—Control R/W 0x0000_0000 13.3.2.28/13-43
0x504–
0xFFF
Reserved, should be cleared — — —
1
This register has separate functions for the host and device operation; the host function is listed first in the table.
Offset 0x100 Access: Read-only
7 0
R CAPLENGTH
W
Reset01000000
Figure 13-2. Capability Registers Length (CAPLENGTH)
Table 13-3. USB Interface Memory Map (continued)
Offset Register Access Reset Section/Page