Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
13-4 Freescale Semiconductor
13.3 Memory Map/Register Definitions
This section provides the memory map and detailed descriptions of all USB interface registers. The
memory map of the USB interface is shown in Table 13-3.
USBDR_STP O Stop. USBDR_STP indicates the end of a transfer on the bus.
State
Meaning
Asserted—USB asserts this signal for 1 clock cycle to stop the data stream
currently on the bus. If USB port is sending data to the PHY, USBDR_STP
indicates the last byte of data was previously on the bus. If the PHY is
sending data to USB port, USBDR_STP forces the PHY to end its transfer,
negate USBDR_DIR and relinquish control of the data bus to the USB port.
Negated—Indicates normal operation.
Timing Synchronous to PHY_CLK.
USBDR_PWR_FAULT I Power fault. USBDR_PWR_FAULT indicates whether a power fault occurred on the USB port
Vbus.
State
Meaning
Asserted—Indicates that a Vbus fault occurred. Applications that support power
switching must shut down Vbus power.
Negated—Indicates normal operation.
Timing Synchronous to PHY_CLK.
USBDR_PCTL0 O Port control 0. USBDR_PCTL0 controls the port status indicator LED 0 when in host mode.
State
Meaning
Asserted—LED on.
Negated—LED off.
Timing Synchronous to PHY_CLK.
USBDR_PCTL1 O Port control 1. USBDR_PCTL1 controls the port status indicator LED 1 when in host mode.
State
Meaning
Asserted—LED on.
Negated—LED off.
Timing Synchronous to PHY_CLK.
USBDR_TXDRXD[0:7] I/O Data bit n. USBDR_TXDRXDn is bit n of the 8-bit (USBDR_TXDRXD7–USBDR_TXDRXD0),
uni-directional data bus used to carry USB, register, and interrupt data between the PHY and
the USB controller.
State
Meaning
Asserted—Data bit n is 1.
Negated—Data bit n is 0.
Timing Synchronous to PHY_CLK.
USBDR_CLK I Clocking signal for ULPI PHY interface.
Table 13-3. USB Interface Memory Map
Offset Register Access Reset Section/Page
USB DR Controller Registers
USB DR Controller—Block Base Address 0x2_3000
0x000–0x0FF Reserved, should be cleared — — —
Table 13-2. ULPI Signal Descriptions (continued)
Signal I/O Description