Information

Universal Serial Bus Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 13-3
13.2 External Signals
This section contains detailed descriptions of all the USB dual-role controller signals. Many of the signals
for the PHY interfaces are muxed onto the same pins in order to reduce pin count. Table 13-1 describes the
signals, indicating which interface supports each signal.
13.2.1 ULPI Interface
The ULPI (UTMI low pin count interface) is a reduced pin-count (12 signals) extension of the UTMI+
specification. Pin count is reduced by converting relatively static signals to register bits, and providing a
bidirectional, generic data bus that carries USB and register data. This interface minimizes pin count
requirements for external PHYs. Table 13-2 describes the signals for the ULPI interface.
Table 13-1. USB External Signals
Signal I/O
USBDR_PWR_FAULT I
USBDR_CLK I
USBDR_DIR I
USBDR_NXT I
USBDR_TXDRXD[0:7] I/O
USBDR_PCTL[0:1] O
USBDR_STP O
Table 13-2. ULPI Signal Descriptions
Signal I/O Description
USBDR_DIR I Direction. USBDR_DIR controls the direction of the data bus. When the PHY has data to
transfer to USB port, it drives USBDR_DIR high to take ownership of the bus. When the PHY
has no data to transfer it drives USBDR_DIR low and monitors the bus for link activity. The PHY
pulls USBDR_DIR high whenever the interface cannot accept data from the link.
State
Meaning
Asserted—PHY has data to transfer to the link.
Negated—PHY has no data to transfer.
Timing Synchronous to PHY_CLK.
USBDR_NXT I Next data. The PHY asserts USBDR_NXT to throttle the data. When USB port is sending data
to the PHY, USBDR_NXT indicates when the current byte has been accepted by the PHY. The
USB port places the next byte on the data bus in the following clock cycle. When the PHY is
sending data to USB port, USBDR_NXT indicates when a new byte is available for USB port
to consume.
State
Meaning
Asserted—PHY is ready to transfer byte.
Negated—PHY is not ready.
Timing Synchronous to PHY_CLK.