Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-31
2. DMA engine writes: TCD.done = 0, TCD.start = 0, TCD.active = 1.
3. DMA engine reads: channel TCD data from local memory to internal register file.
4. The source to destination transfers are executed as follows:
a) read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003)
b) write_word(0x2000)  first iteration of the minor loop
c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007)
d) write_word(0x2004)  second iteration of the minor loop
e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b)
f) write_word(0x2008)  third iteration of the minor loop
g) read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f)
h) write_word(0x200c)  last iteration of the minor loop
5. DMA engine writes: TCD.saddr = 0x1010, TCD.daddr = 0x2010, TCD.citer = 1.
6. DMA engine writes: TCD.active = 0.
7. The channel retires  one iteration of the major loop.
The DMA goes idle or services next channel.
8. Software sets the TCD.start bit of the channel for activation. The channel is selected by arbitration
for servicing.
9. DMA engine writes: TCD.done = 0, TCD.start = 0, TCD.active = 1.
10. DMA engine reads: channel TCD data from local memory to internal register file.
11. The source to destination transfers are executed as follows:
a) read_byte(0x1010), read_byte(0x1011), read_byte(0x1012), read_byte(0x1013)
b) write_word(0x2010)  first iteration of the minor loop
c) read_byte(0x1014), read_byte(0x1015), read_byte(0x1016), read_byte(0x1017)
d) write_word(0x2014)  second iteration of the minor loop
e) read_byte(0x1018), read_byte(0x1019), read_byte(0x101a), read_byte(0x101b)
f) write_word(0x2018)  third iteration of the minor loop
g) read_byte(0x101c), read_byte(0x101d), read_byte(0x101e), read_byte(0x101f)
h) write_word(0x201c)  last iteration of the minor loop  major loop complete
12. DMA engine writes:
TCD.saddr = 0x1000, TCD.daddr = 0x2000, TCD.citer = 2 (TCD.biter).
13. DMA engine writes: TCD.active = 0, TCD.done = 1, DMAINT[n] = 1.
14. The channel retires  major loop complete.
The DMA goes idle or services the next channel.