Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-29
channel into its internal address path module. As the TCD is being read, the first transfer is initiated on the
AHB bus unless a configuration error is detected. Transfers from the source (as defined by the source
address, TCD.saddr) to the destination (as defined by the destination address, TCD.daddr) continue until the
specified number of bytes (TCD.nbytes) have been transferred. When the transfer is complete, the DMA
engine's local
TCD.saddr, TCD.daddr, and TCD.citer are written back to the main TCD memory and any
minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post processing
is executed, that is, interrupts, major loop channel linking, and scatter/gather operations, if enabled.
12.5.2 DMA Programming Errors
The DMA performs various tests on the transfer control descriptor to verify consistency in the descriptor
data. Most programming errors are reported on a per channel basis with the exception of channel priority
error and CPE in the DMAES register.
For all error types other than channel priority errors, the channel number causing the error is recorded in
the DMAES register. If the error source is not removed before the next activation of the problem channel,
the error is detected and recorded again.
In general, if priority levels are not unique, the highest channel priority that has an active request is
selected, but the lowest numbered channel with that priority is selected by arbitration and executed by the
DMA engine. The error interrupts and error reporting is associated with the selected channel.
12.6 DMA Transfer
This section discusses the procedures for single and multiple requests.
12.6.1 Single Request
To perform a simple transfer of n bytes of data with one activation, set the major loop to one
(TCD.citer = TCD.biter = 1). The data transfer begins after the channel service request is acknowledged
and the channel is selected to execute. Once the transfer is complete, the TCD.done bit is set and an interrupt
is generated, if properly enabled.
For example, the following TCD entry is configured to transfer 16 bytes of data. The DMA is programmed
for one iteration of the major loop transferring 16 bytes per iteration. The source memory has a byte wide
memory port located at 0x1000. The destination memory has a word wide port located at 0x2000. The
address offsets are programmed in increments to match the size of the transfer; one byte for the source and
four bytes for the destination.
The final source and destination addresses are adjusted to return to their beginning values:
•
TCD.citer = TCD.biter = 1
•
TCD.nbytes = 16
•
TCD.saddr = 0x1000
• TCD.soff = 1
•
TCD.ssize = 0
• TCD.slast = –16