Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-27
This source read/destination write processing continues until the inner minor byte count has been
transferred.
Figure 12-24. DMA Operation—Part 2
Once the inner minor byte count has been moved, the final phase of the basic data flow is performed. In
this segment, the addr_path logic performs the required updates to certain fields in the channel’s TCD, for
example, saddr, daddr, citer. If the outer major iteration count is exhausted, then there are additional
operations which are performed. These include the final address adjustments and reloading of the biter
field into the citer. Additionally, assertion of an optional interrupt request occurs at this time, as does a
possible fetch of a new TCD from memory using the scatter/gather address pointer included in the
dma_ipi_int[n – 1:0]
Register Interface
DMA
AHB Interface
pmodel_charb
wdata[31:0]
addr
rdata[31:0]
SRAM Transfer Control
Descriptor
(TCD)
DMA Engine
0
j
j+1
n–1
controladdr_pathdata_path