Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor lvii
About This Book
This reference manual defines the functionality of the MPC8308. The device is a cost-effective,
low-power, highly integrated host processor that addresses the requirements of networking applications
such as low-end printing, smart grid, home energy gateways, data concentrators, wireless LAN access
points, femto base stations, and industrial applications, such as industrial control and factory automation.
The MPC8308 extends the PowerQUICC II Pro family, adding a higher performance CPU, additional
functionality, and faster interfaces while addressing the requirements related to time-to-market, price,
power consumption, and package size.
Audience
It is assumed that the reader understands operating systems, microprocessor system design, and the basic
principles of RISC processing.
Organization
Following is a summary and a brief description of the major parts of this reference manual:
• Chapter 1, “Overview,” provides a high-level description of features and functionality of the
MPC8308. It describes the device, its interfaces, and the programming model. The functional
operation of the device, with emphasis on peripheral functions, is also described.
• Chapter 2, “Signal Descriptions,” provides a listing of all the external signals, cross-references for
signals that serve multiple functions, their functional blocks, and I/O states.
• Chapter 3, “Memory Map,” describes the memory map of the device. An overview of the local
address map is provided. Next, a complete listing of all memory-mapped registers is provided, with
cross references to the sections detailing descriptions of each.
• Chapter 4, “Reset, Clocking, and Initialization,” describes the hard and soft resets, the power-on
reset (POR) sequence, power-on reset configuration, clocking, and initialization of the device.
• Chapter 5, “System Configuration,” provides an overview of several functions that control the
local access windows, system configuration, software watchdog, real time clock, periodic and
general purpose timers, power management, protection, and general utilities.
• Chapter 6, “Arbiter and Bus Monitor,” provides an overview of the arbiter in the device. Also, it
describes the configuration, control, and status registers of the arbiter.
• Chapter 7, “e300 Processor Core Overview,” provides an overview of the basic functionality of the
processor core and briefly describes how the functional units interact.
• Chapter 8, “Integrated Programmable Interrupt Controller (IPIC),” describes the IPIC interrupt
protocol, various types of interrupt sources controlled by the IPIC unit, and the IPIC registers with
some programming guidelines. It also provides a definition of the external interrupt signals and