Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-25
— data_path: This module implements the actual bus master read/write data path. It includes
32 bytes of register storage (matching the maximum transfer size) and the necessary mux logic
to support any required data alignment.
— pmodel_charb: This module implements the first section of DMA programming model as well
as the channel arbitration logic. The programming model registers are connected to the register
interface (not shown). The dma_ipi_int[n] outputs are also connected to this module (via the
control logic).
— control: This module provides all the control functions for the DMA engine. For data transfers
where the source and destination sizes are equal, the DMA engine performs a series of source
read, destination write operations until the number of bytes specified in the inner minor loop
byte count has been moved. For descriptors where the sizes are not equal, multiple access of
the smaller size data are required for each reference of the larger size. As an example, if the
source size references 16-bit data and the destination is 32-bit data, two reads are performed,
then one 32-bit write.
• transfer_control_descriptor local memory
— memory controller: This logic implements the required dual-ported controller, handling
accesses from both the DMA engine as well as references from the register interface. As noted
earlier, in the event of simultaneous accesses, the DMA engine is given priority and the register
interface transaction is stalled.
— memory array: The TCD is implemented using a single-ported, synchronous compiled RAM
memory array.
12.4.2 DMA Basic Data Flow
The basic flow of a data transfer can be partitioned into three segments. As shown in Figure 12-23, the first
segment involves the channel service request. Software requests the channel service by setting the
TCD.start bit. In the next cycle, the channel arbitration is performed, either using the fixed-priority or
round-robin algorithm. After the arbitration is complete, the activated channel number is sent through the
address path (addr_path) and converted into the required address to access the TCD local memory. Next,
the TCD memory is accessed and the required descriptor read from the local memory and loaded into the
DMA engine addr_path.channel_{x,y} registers. The TCD memory is organized 64-bits in width to