Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 12-23
24–16 biter[8–0] Beginning major iteration count. This is the initial value copied into the citer field or citer.linkch
field when the major loop is completed. The citer fields controls the iteration count and linking
during channel execution. This 9 or 15-bit counter presents the beginning major loop count for
the channel. As the major iteration count is exhausted, the contents of the entire 16 bit biter entry
is reloaded into the 16 bit citer entry. When the biter field is initially loaded by software, it must be
set to the same value as that contained in the citer field. If the channel is configured to execute
a single service request, the initial values of biter and citer should be 0x0001.
15–14 bwc[1–0] Bandwidth control. This two-bit field provides a mechanism to effectively throttle the amount of
bus bandwidth consumed by the DMA. In general, as the DMA processes the inner minor loop,
it continuously generates read/write, read/write, ..., sequences until the minor count is exhausted.
To minimize start-up latency, bandwidth control stalls are suppressed for the first two AHB bus
cycles and after the last write of each minor loop. The dynamic priority elevation setting elevates
the priority of the DMA as seen by the system arbiter for the executing channel. Dynamic priority
elevation is suppressed during the first two AHB bus cycles.
00 No DMA engine stalls
01 dynamic priority elevation
10 DMA engine stalls for four cycles after each R/W
11 DMA engine stalls for eight cycles after each R/W
13–8 major.linkch
[5–0]
Link channel number. If (TCD.major.e_link = 0) then No channel-to-channel linking (or
chaining) is performed after the outer major loop counter is exhausted. Otherwise, after the major
loop counter is exhausted, the DMA engine initiates a channel service request at the channel
defined by major.linkch[5:0] by setting that channel’s TCD.start bit.
The value contained in major.linkch[5:0] must not exceed the number of implemented channels.
7 done Channel done. This flag indicates the DMA has completed the outer major loop. It is set by the
DMA engine as the citer count reaches zero; it is cleared by software, or the hardware when the
channel is activated. This bit must be cleared in order to write the major.e_link or e_sg bits.
6 active Channel active. This flag signals the channel is currently in execution. It is set when channel
service begins, and is cleared by the DMA engine as the inner minor loop completes or if any
error condition is detected.
5 major.e_link Enable channel-to-channel linking on major loop complete. As the channel completes the outer
major loop, this flag enables the linking to another channel, defined by major.linkch[5:0]. The link
target channel initiates a channel service request via an internal mechanism that sets the
TCD.start bit of the specified channel. To support the dynamic linking coherency model, this
field is forced to zero when written to while the TCD.done bit is set.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
4 e_sg Enable scatter/gather processing. As the channel completes the outer major loop, this flag
enables scatter/gather processing in the current channel. If enabled, the DMA engine uses
dlast_sga as a memory pointer to a 0-modulo-32 address containing a 32-byte data structure
which is loaded as the transfer control descriptor into the local memory. To support the dynamic
scatter/gather coherency model, this field is forced to zero when written to while the TCD.done
bit is set.
0 The current channel’s TCD is “normal” format.
1 The current channel’s TCD specifies a scatter gather format. The dlast_sga field provides a
memory pointer to the next TCD to be loaded into this channel after the outer major loop
completes its execution.
3—Reserved
Table 12-23. TCD Word 7 (TCD.{biter, control/status}) Field Descriptions (continued)
Bits Name Description