Information

DMA Controller (DMAC)
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
12-20 Freescale Semiconductor
Table 12-19 describes the TCD word 3 fields.
Figure 12-19 shows the TCD word 4 field.
Table 12-20 describes the TCD word 4 fields.
Figure 12-20 shows the TCD word 5 field.
Table 12-19. TCD Word 3 (TCD.slast) Field Descriptions
Bits Name Description
31–0 slast Last source address adjustment. Adjustment value added to the source address at the completion of the
outer major iteration count. This value can be applied to ‘restore’ the source address to the initial value, or
adjust the address to reference the next data structure.
Offset DMA_Offset = 0x1000 + (32 x n) + 0x10 Access: Read/Write
31 16
R
daddr[31–16]
W
Reset All zeros
15 0
R
daddr[15–0]
W
Reset All zeros
Figure 12-19. TCD Word 4 (TCDn.daddr) Field
Table 12-20. TCD Word 4 (TCD.daddr) Field Description
Bits Name Description
31–0 daddr Destination address. Memory address pointing to the destination data.
Offset DMA_Offset = 0x1000 + (32 x n) + 0x14 Access: Read/Write
31 30 25 24 16
R
citer.
e_link
citer[14–9} or citer.linkch[5–0] citer[8–0]
W
Reset All zeros
15 0
R
doff[15–0]
W
Reset All zeros
Figure 12-20. TCD Word 5 (TCDn.{citer, doff}) Fields